Automatic semiconductor wafer sorter/prober with extended optical inspection

• US 6,021,380 A
• Filed: 07/02/1997
• Issued: 02/01/2000
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Scanis, Inc.
• Original Assignee: Scanis, Inc.
• Inventors: Chapman, Robert L., Fredriksen, T. Roland
• Primary Examiner(s): Peeso, Thomas R.
• Application Number:
  US08/886,066
• Time in Patent Office: 944 Days
• Field of Search: 702/35, 356/237.2, 356/390, 600/407
• US Class Current: 702/35
• CPC Class Codes: G01N 21/88 Investigating the presence of flaws or contamination
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die

Abstract

A method and apparatus for visually inspecting and sorting semiconductor wafers and the individual microcircuits or chips thereon. The preferred embodiment employs a scanner to obtain a virtual reality image of the wafer and all chips are identified and sorted by applying high-speed image processing routines. The resulting wafer map provides unique image controlled chip coordinates making the chips identifiable even after the chips are diced apart. The wafer may contain different kinds of chips in irregular patterns. A gross-defect, visual inspection sorts out defective chips based on image completeness maximizing the yield and throughput. All inspections and identifications are performed on the virtual wafer or chip images scanned into a computer memory with full physical wafer correlation but without having to manipulate the wafer. The inspection time is, therefore, largely free due to overlapping it by regular transport operations.

Claims

1. In a method for investigating electronic circuit devices for manufacturing defects, the steps of:

(a) converting intuitive criteria used to investigate an electronic circuit device for manufacturing defects to specific numerical criteria;

(b) programming a computer with said criteria;

(c) acquiring information in said programmed computer defining an electronic circuit device by scanning in an image of said device and operating on said virtual images rather than manipulating the physical device;

(d) using said computer to apply said specific numerical criteria defined by said program to said information to identify regions of said electronic circuit device to be investigated, said information defining a manufacturing defect.

2. The method of claim 1 wherein said specific numeric criteria that are applied to segregated regions of said electronic circuit device having manufacturing defects which contain defect characteristics exceeding the standards required for further use of said regions of said electronic circuit device for processing into electronic circuit device products.

3. The method of claim 1 together with the step of introducing an image controlled coordinate reference system allowing individual electronic circuit devices to be reliably re-identified throughout the processing steps.

4. The method of claim 1 wherein said electronic circuit devices are semiconductor wafers together with the step of automatically generating a wafer map from a scanned wafer image requiring no physical manipulation of the wafer and using said map to position a CCD camera adjacent said wafer to obtain high resolution images for a detailed chip inspection.

5. The method of claim 1 wherein said electronic circuit devices are semiconductor wafers together with the step of aligning the wafer according to die pattern.

6. In a method for investigating semi-conductor wafers for manufacturing defects, the steps of:

(a) acquiring information from an image defining said semi-conductor wafer with opto-electronic means, including the step of generating a digital representation of said image;

(b) analyzing said information by applying pre-selected criteria to said information to identify regions of said semi-conductor wafer by said information having a manufacturing defect;

said step of analyzing including detecting digital information in said representation defining manufacturing defects in said semi-conductor wafer, and

detecting digital information in said representation defining said defects.

7. A gross defect, optical inspection unit for chips on a semiconductor wafers comprising:

means for aligning the wafer according to the die pattern;

means for generating a unique map for each wafer;

means for sorting the chips by direct image analysis into testable and not testable categories; and

means for selecting for further testing only those chips sorted as testable.