Video FIFO overflow control method that blocks video encoder data when overflow is imminent and resumes flow when frames sizes have returned to nominal size

• US 6,021,449 A
• Filed: 08/01/1997
• Issued: 02/01/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chow, Robert, Dobson, Hamish D.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US08/904,773
• Time in Patent Office: 914 Days
• Field of Search: 710/1, 710/57, 348/390, 348/419, 711/154, 370/517, 358/133
• US Class Current: 710/57
• CPC Class Codes: H04N 21/23406 involving management of server-side video buffer
• CPC Class Codes: H04N 21/23605 Creation or processing of packetized elementary streams [PES]
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18

Abstract

A multimedia terminal having a host processor, an audio and video encoder and a system time clock. The encoders are input as digital video elementary frames into a multiplexer. The multiplexer includes a mux processor, a video FIFO and a video mux logic circuit coupled to both the mux processor and the video FIFO. Mux logic is operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in the FIFO to form the payload of a transport packet.

Claims

1. A multimedia terminal having a host processor, an encoder, a system clock (STC), the output of said encoder being input as compressed digital video frames into a multiplexer, said multiplexer comprising:

(a) a mux processor for packetizing the compressed video frames;

(b) a FIFO buffer coupled to the encoder operative to buffer digital video data and responsive to the MUX processor to output data from the buffer to the MUX processor;

(c) a video mux logic circuit coupled to said mux processor and said video FIFO buffer, operative to provide status signals to the MUX processor concerning FIFO buffer status, to monitor video FIFO buffer fullness and to signal the mux processor when there is sufficient video data in said video FIFO buffer to form the payload of a transport packet in accordance with an encoder/decoder protocol.

2. A terminal according to claim 1 wherein the encoder/decoder protocol is an MPEG-2 protocol and said MUX processor packetizes said units by adding PES headers and time stamps as specified by the host processor.

3. A terminal according to claim 1, wherein said video mux logic circuit includes means for signaling the mux processor when the video elementary stream has an excessively high rate of data and rate control by the MUX processor is required.

4. A terminal according to claim 1, wherein said video mux logic circuit includes means for signaling said mux processor to drop an elementary video stream frame in response to the channel bandwith being exceeded by the elementary stream video data resulting in the data into the video FIFO buffer being backed up.

5. A method of controlling video FIFO buffer overflows caused by a high rate of compressed digital video signals being sent by a video encoder, comprising:

(a) detecting imminent video FIFO buffer overflows by monitoring the output of the video encoder prior to entry into the video FIFO buffer;

(b) blocking all subsequent compressed data from entering the video FIFO buffer;

(c) monitoring frame sizes out of said video encoder while the compressed data is blocked from entering the video FIFO buffer; and

(d) allowing data to begin entering said video FIFO buffer again when frame-sizes from said encoder have returned to a nominal size.

6. A method according to claim 5, wherein said detecting step comprises detecting start codes at an input to said video FIFO so that frame sizes may be monitored even when data is not being allowed into said video FIFO.

7. A multimedia terminal having a host processor, an encoder, a system clock (STC), the output of said encoder being input as compressed digital video frames into a multiplexer, said multiplexer comprising:

(a) a mux processor;

(b) a FIFO buffer operative to buffer digital video data; and

(c) a video mux logic circuit coupled to said mux processor and said video FIFO, operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in said video FIFO to form the payload of a transport packet in accordance with an encoder/decoder protocol wherein said video mux logic circuit signals said mux processor when a video start-code is in the transport packet payload that it is about to read.

8. A multimedia terminal having a host processor, an encoder, a system clock (STC), the output of said encoder being input as compressed digital video frames into a multiplexer, said multiplexer comprising:

(a) a mux processor;

(b) a FIFO buffer operative to buffer digital video data; and

(c) a video mux logic circuit cupled to said mux processor and said video FIFO, operative to minitor vidor FIFO fullness and to signal the mux processor when there is sufficient video data in said video FIFO to form the payload of a transport packet in accordance with an encoder/decoder protocol wherein said video mux logic includes a video state machine coupled to said video FIFO operative to track video start-codes through said video FIFO.

9. A multimedia terminal having a host processor, an encoder, a system clock (STC), the output of said encoder being input as compressed digital video frames into a multiplexer, said multiplexer comprising:

(a) a mux processor;

(b) a FIFO buffer operative to buffer digital video data; and

(c) a video mux logic circuit coupled to said mux processor and said video FIFO, operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in said video FIFO to form the payload of a transport packet in accordance with an encoder/decoder protocol; and

(d) video FIFO write logic coupled to said video FIFO and operative to control writing of compressed data to said video FIFO.

10. A terminal according to claim 9, including a video start code detect state machine coupled to said compressed data, a video start code position tracking circuit operative to track the position of a video start code marking the beginning of an elementary video stream, a vidor FIFO buffer fullness counter having an input coupled to an output of said encoder and an output coupled to said video FIFO buffer write logic circuit, operative to measure the amount of video data in said video FIFO buffer, a video start code position coupled to an output of said video FIFO buffer fullness counter operative to record the advance of said video start code through said video FIFO buffer, whereby said multiplexer is provided with advance knowledge of whether a ones frame begins with a next available packet of elementary video stream data.

11. A method of controlling video FIFO overflows caused by a high rate of compressed digital video signals being sent by a video encoder, comprising:

(a) detecting imminent video FIFO overflows;

(b) blocking all subsequent compressed data from entering the video FIFO;

(c) monitoring frame sizes out of said video encoder;

(d) allowing data to begin entering said video FIFO when frame-sizes from said encoder have returned to a nominal size; and

(e) informing said mux processor of elementary video stream frame drop events so that it may insert corresponding error codes into the elementary video stream.