Data processing system having memory sub-array redundancy and method therefor
First Claim
1. A data processing system, comprising:
- a central processing unit for providing a plurality of address values and a plurality of data values;
a memory coupled to the central processing unit for receiving the plurality of address values and communicating the plurality of data values;
a redundant memory array coupled to the central processing unit for receiving the plurality of address values and selectively communicating the plurality of data values, the redundant memory array, comprising;
a plurality of memory cells; and
a wordline decoder coupled only to the plurality of memory cells; and
a multiplexer coupled to the memory for receiving a first data value and coupled to the redundant memory array for receiving a first redundant data value, the multiplexer selectively providing one of the first data value and the first redundant data value as a data output value.
1 Assignment
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Accused Products
Abstract
One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each of these redundant sub-arrays includes a separate and independent wordline decoder (202), bitline decoder (206), and input/output circuit (208). Furthermore, the memory to which the redundant sub-array is added is typically an on-chip memory which is organized into bit-slice sub-arrays. The bit-slice organization of the memory allows the redundant sub-array to be chained together with the on-chip memory. Data-in/data-out multiplexers are used to steer bit-slices of the data around the defective sub-arrays.
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Citations
14 Claims
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1. A data processing system, comprising:
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a central processing unit for providing a plurality of address values and a plurality of data values; a memory coupled to the central processing unit for receiving the plurality of address values and communicating the plurality of data values; a redundant memory array coupled to the central processing unit for receiving the plurality of address values and selectively communicating the plurality of data values, the redundant memory array, comprising; a plurality of memory cells; and a wordline decoder coupled only to the plurality of memory cells; and a multiplexer coupled to the memory for receiving a first data value and coupled to the redundant memory array for receiving a first redundant data value, the multiplexer selectively providing one of the first data value and the first redundant data value as a data output value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processing system, comprising:
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a central processing unit for providing a plurality of address values and a plurality of data values; a memory coupled to the central processing unit for receiving the plurality of address values and communicating the plurality of data values; a redundant memory array coupled to the central processing unit for receiving the plurality of address values and selectively communicating the plurality of data values, the redundant memory array, comprising; a plurality of memory cells; and a wordline decoder coupled only to the plurality of memory cells; a redundancy control circuit coupled to the central processing unit to receive the plurality of address values, the redundancy control circuit providing a redundant control signal to indicate a portion of the memory is defective; and a multiplexer coupled to the memory for receiving a first data value, coupled to the redundant memory array for receiving a first redundant data value, and coupled to the redundancy control circuit for receiving the redundant control signal, the multiplexer providing the first data value as a data output value when the redundant control signal is in a first logic state and the multiplexer providing the first redundant data value as the data output value when the redundant control signal is in a second logic state.
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11. A data processing system, comprising:
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a central processing unit for providing a plurality of address values and a plurality of data values; a memory coupled to the central processing unit for receiving the plurality of address values and communicating the plurality of data values; a redundant memory array coupled to the central processing unit for receiving the plurality of address values and selectively communicating the plurality of data values, the redundant memory array, comprising; a plurality of memory cells; and a wordline decoder coupled only to the plurality of memory cells; a redundancy control circuit coupled to the central processing unit to receive the plurality of address values, the redundancy control circuit providing a redundant control signal to indicate a portion of the memory is defective; and a multiplexer coupled to the central processing unit for receiving the plurality of data values and coupled to the redundancy control circuit for receiving the redundant control signal, the multiplexer providing a first one of the plurality of data values to the memory when the redundant control signal is in a first logic state and providing the first one of the plurality of data values to the redundant memory array when the redundant control signal is in a second logic state.
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12. A data processing system comprising:
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a central processing unit for providing a plurality of address values and a plurality of data values; a memory coupled to the central processing unit for receiving the plurality of address values and communicating the plurality of data values; a redundant memory array coupled to the central processing unit for receiving the plurality of address values and selectively communicating the plurality of data values, the redundant memory array, comprising; a plurality of memory cells; and a wordline decoder coupled only to the plurality of memory cells, wherein the redundant control signal enables the redundant memory to a stored data value when the plurality of address values correspond to the portion of the memory which is defective.
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13. A method for operating a data processing system, comprising the steps of:
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providing a plurality of address values and a plurality of data values; receiving by a memory the plurality of address values and communicating the plurality of data values; receiving by a redundant memory array the plurality of address values and selectively communicating the plurality of data values; receiving by a multiplexer a first data value from the memory and receiving by the multiplexer a first redundant data value from the redundant memory array; and selectively providing by the multiplexer one of the first data value and the first redundant data value as a data output value.
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14. A memory system, comprising:
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a memory, comprising; first interface means for receiving a plurality of address values and for selectively communicating a plurality of data values; a plurality of memory cells; and a wordline decoder coupled to the first interface means for selectively receiving a first one of the plurality of address values and accessing a portion of the plurality of memory cells corresponding to the first one of the plurality of address values; a redundant memory, comprising; second interface means for receiving the plurality of address values and for selectively communicating the plurality of data values; a plurality of redundant memory cells; and a redundant wordline decoder coupled to the second interface means for selectively receiving the first one of the plurality of address values and accessing a portion of the plurality of redundant memory cells corresponding to the first one of the plurality of address values; and a multiplexer coupled to the memory for receiving a first data value and coupled to the redundant memory array for receiving a first redundant data value, the multiplexer selectively providing one of the first data value and the first redundant data value as a data output value.
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Specification