Method for reducing via inductance in an electronic assembly and article

• US 6,021,564 A
• Filed: 09/23/1998
• Issued: 02/08/2000
• Est. Priority Date: 11/08/1996
• Status: Expired due to Term

• Current Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Original Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Inventors: Hanson, David A.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US09/159,140
• Time in Patent Office: 503 Days
• Field of Search: 29/825, 29/830, 29/852, 29/853, 427/97, 427/98
• US Class Current: 29/852
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/0792 Means against parasitic impedance; Means against eddy currents
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Claims

1. A method for reducing via inductance in a laminated substrate, said method comprising the following steps:

providing a laminated substrate having alternating conductive and dielectric layers, said laminated substrate including at least a first conductive layer, a first dielectric layer affixed to a surface of the first conductive layer, a second conductive layer affixed to a surface of the first dielectric layer, a second dielectric layer affixed to a surface of the second conductive layer, a third conductive layer affixed to a surface of the second dielectric layer, a third dielectric layer affixed to a surface of the third conductive layer, and a fourth conductive layer affixed to a surface of the third dielectric layer;

forming a first conductive via having an entrance diameter of 75 μ

m or less in a location in said first conductive and said first dielectric layers, said first conductive via electrically connecting said first and second conductive layers;

forming a second conductive via having an entrance diameter of 75 μ

m or less in a location in said second dielectric layer offset from said location of said first conductive via, said second conductive via electrically connecting said second and said third conductive layers; and

forming a third conductive via having an entrance diameter of 75 μ

m or less in a location in said fourth conductive and said third dielectric layers, said location of said third conductive via being substantially vertically aligned with said location of said first conductive via, said third conductive via electrically connecting said third and said fourth conductive layers;

defining an electrical signal path having a first portion in said first conductive layer routed in a direction toward the first conductive via, a second portion in said second conductive layer routed in a direction toward the second conductive via, a third portion in said third conductive layer routed in a direction toward said third conductive via and a fourth portion in said fourth conductive layer;

said location of said second conductive via being such that a mutual inductance formed by the first portion of the electrical signal path with the second portion of the electrical signal path cancels a mutual inductance formed by the second portion of the electrical signal path with the first portion of the electrical signal path, and such that a mutual inductance formed by the second portion of the electrical signal path with the third portion of the electrical signal path cancels a mutual inductance formed by the third portion of the electrical signal path with the second portion of the electrical signal path, and such that a mutual inductance formed by the third portion of the electrical signal path with the fourth portion of the electrical signal path cancels a mutual inductance formed by the fourth portion of the electrical signal path with the third portion of the electrical signal path.

2. A method of making an integrated circuit chip package, said method comprising the following steps:

providing a laminated substrate having alternating conductive and organic dielectric layers, said laminated substrate including at least a first conductive layer, a first organic dielectric layer affixed to a surface of the first conductive layer, a second conductive layer affixed to a surface of the first organic dielectric layer, a second organic dielectric layer affixed to a surface of the second conductive layer, a third conductive layer affixed to a surface of the second organic dielectric layer, a third organic dielectric layer affixed to a surface of the third conductive layer, and a fourth conductive layer affixed to a surface of the third organic dielectric layer;

forming a first conductive via by laser drilling in a location in said first conductive and said first organic dielectric layers, said first conductive via electrically connecting said first and second conductive layers;

forming a second conductive via by laser drilling in a location in said second organic dielectric layer offset from said location of said first conductive via, said second conductive via electrically connecting said second and said third conductive layers; and

forming a third conductive via by laser drilling in a location in said fourth conductive and said third organic dielectric layers, said location of said third conductive via being substantially vertically aligned with said location of said first conductive via, said third conductive via electrically connecting said third and said fourth conductive layers;

defining an electrical signal path having a first portion in said first conductive layer routed in a direction toward the first conductive via, a second portion in said second conductive layer routed in a direction toward the second conductive via, a third portion in said third conductive layer routed in a direction toward said third conductive via and a fourth portion in said fourth conductive layer;

said location of said second conductive via being such that a mutual inductance formed by the first portion of the electrical signal path with the second portion of the electrical signal path cancels a mutual inductance formed by the second portion of the electrical signal path with the first portion of the electrical signal path, and such that a mutual inductance formed by the second portion of the electrical signal path with the third portion of the electrical signal path cancels a mutual inductance formed by the third portion of the electrical signal path with the second portion of the electrical signal path, and such that a mutual inductance formed by the third portion of the electrical signal path with the fourth portion of the electrical signal path cancels a mutual inductance formed by the fourth portion of the electrical signal path with the third portion of the electrical signal path.

3. A method for reducing via inductance in a laminated substrate, said method comprising the following steps:

providing a laminated substrate having alternating conductive and dielectric layers, said laminated substrate including at least a first conductive layer, a first dielectric layer affixed to a surface of the first conductive layer, a second conductive layer affixed to a surface of the first dielectric layer, a second dielectric layer affixed to a surface of the second conductive layer, and a third conductive layer affixed to a surface of the second dielectric layer;

forming a first conductive via by laser drilling in a location in said first conductive and said first dielectric layers, said first conductive via electrically connecting said first and second conductive layers, said first conductive via having an entrance diameter of 75 μ

m or less; and

forming a second conductive via by laser drilling in a location in said second dielectric layer offset from said location of said first conductive via, said second conductive via electrically connecting said second and said third conductive layers, said second conductive via having an entrance diameter of 75 μ

m or less;

defining an electrical signal path having a first portion in said first conductive layer routed in a direction toward the first conductive via, and a second portion in said second conductive layer routed in a direction toward the second conductive via;

wherein said location of said second conductive via is such that a mutual inductance formed by the first portion of the electrical signal path with the second portion of the electrical signal path cancels a mutual inductance formed by the second portion of the electrical signal path with the first portion of the electrical signal path.