Process for manufacturing solder leads on a semiconductor device package

• US 6,022,758 A
• Filed: 02/21/1997
• Issued: 02/08/2000
• Est. Priority Date: 07/10/1994
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Shellcase Ltd. (Adeia Inc.)
• Inventors: Badehi, Pierre
• Primary Examiner(s): Graybill, David E.
• Application Number:
  US08/765,473
• Time in Patent Office: 1,082 Days
• Field of Search: 438/108, 438/614, 438/612, 438/615, 438/613, 438/617, 438/667, 438/675
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0101 Neon [Ne]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A process of forming a packaged integrated circuit by aperturing a discrete packaging layer attached on a silicon substrate. A plurality of solder leads are formed on the layer. Electrical connections are formed from the leads to pads on the substrate.

Claims

1. A method of forming a packaged integrated circuit comprising:

providing a silicon substrate;

forming at least one metal layer onto said silicon substrate including a plurality of pads;

providing a discrete packaging layer;

aperturing the discrete packaging layer to provide an apertured discrete packaging layer having apertures located in locations corresponding to locations of said plurality of pads;

attaching said apertured discrete packaging layer over said at least one metal layer so that said apertures communicate with said pads;

forming a plurality of solder leads on an exterior surface of said at least one packaging layer; and

forming electrical connections directly from individual ones of said plurality of pads to individual ones of said solder leads.

2. A method according to claim 1 and wherein said electrical connections are formed following attachment of said at least one packaging layer to said substrate.

3. A method according to claim 1 and wherein said steps of:

forming at least one metal layer, attaching at least one packaging layer over said at least one metal layer, forming a plurality of solder leads on an exterior surface of said at least one packaging layer and forming electrical connections directly from individual ones of said plurality of pads to individual ones of solder leads are carried out waferwise.

4. A method according to claim 1 and wherein said steps of:

forming at least one metal layer, attaching at least one packaging layer over said at least one metal layer, forming a plurality of solder leads on an exterior surface of said at least one packaging layer and forming electrical connections directly from individual ones of said plurality of pads to individual ones of solder leads are carried out diewise.