Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions

• US 6,022,771 A
• Filed: 01/25/1999
• Issued: 02/08/2000
• Est. Priority Date: 01/25/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wann, Hsing-Jen C., Ma, William Hsioh-Lien
• Primary Examiner(s): Booth, Richard
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US09/236,691
• Time in Patent Office: 379 Days
• Field of Search: 438/300, 438/301, 438/303, 438/305, 438/230, 438/978, 257/750, 257/347, 257/382
• US Class Current: 438/230
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

Claims

1. A method for fabricating a semiconductor device having shallow junctions comprising:

providing a semiconductor substrate having source and drain regions and polysilicon gate regions;

depositing selective silicon on the source and drain regions;

providing dopant into the source and drain regions forming shallow junctions;

forming first insulating sidewall spacers on sidewalls of the gate regions;

wherein the first insulating sidewall spacers are formed by thermal oxidation of exposed silicon and polycrystalline silicon creating taper-shaped isolation where the source and drain regions meet the gate regions;

forming second insulating spacers on the first insulating sidewall spacers;

siliciding the top surfaces of the source and drain regions.

2. The method of claim 1 wherein the selective silicon layer is doped and the shallow junctions are formed by driving in dopant from the selective silicon into the source and drain regions.

3. The method of claim 2 which comprises employing a short rapid thermal anneal for driving in the dopant.

4. The method of claim 3 wherein the short rapid thermal anneal is carried out at temperatures of about 800 to about 1200 for about 0.05 to about 1 minute.

5. The method of claim 1 wherein the selective silicon layer is undoped and the shallow junctions are formed by implanting dopant ions into the source and drain regions.

6. The method of claim 1 wherein the shallow junctions are less than 200 Å

.

7. The method of claim 1 wherein the shallow junctions are about 50 to about 150 Å

.

8. The method of claim 1 wherein the first insulating sidewall spacers are about 20 to about 100 Å

thick.

9. The method of claim 1 wherein the second insulating sidewall spacers are selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride and mixtures thereof.

10. The method of claim 9 wherein the second insulating sidewall spacers are about 500 to about 2000 Å

thick.

11. The method of claim 1 wherein said silicide forming metal is selected from the group consisting of tungsten, titanium, cobalt, nickel and mixtures thereof.

12. The method of claim 1 which further comprises gate insulation between the substrate and the gate regions.

13. The method of claim 1 which further comprises providing sidewall insulating layers on sidewalls of the gate regions prior to depositing the selective silicon layer.

14. The method of claim 13 which further comprises removing the sidewall insulating layer after forming the shallow junctions and prior to forming the first insulating sidewall spacers.

15. The method of claim 14 wherein the sidewall insulating layer is about 10 to about 300 Å

thick.

16. The method of claim 1 which further comprises providing insulating cap on the gate regions.

17. The method of claim 16 wherein the insulating cap is added prior to depositing the selective silicon on the source and drain regions.

18. The method of claim 1 which further comprises providing a second selective silicon layer on exposed monocrystalline silicon surface s above source and drain regions.

19. The method of claim 18 wherein the second selective silicon layer is provided subsequent to forming the second could insulating spacers.