Input/output connection structure of a semiconductor device

• US 6,023,080 A
• Filed: 02/11/1998
• Issued: 02/08/2000
• Est. Priority Date: 02/12/1997
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kojima, Haruo
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/022,123
• Time in Patent Office: 727 Days
• Field of Search: 257/692, 257/728, 257/784, 257/783, 257/734, 257/743, 257/744, 257/745, 257/275, 257/604, 257/664, 333/247, 333/246, 333/161, 333/276, 333/277
• US Class Current: 257/275
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device comprises a dielectric substrate formed on a metal carrier, a semiconductor chip formed on the dielectric substrate and having a first electrode, a microstrip line formed on the dielectric substrate and having a second electrode to be connected to the first electrode, and wires, having different lengths, for connecting the first and second electrodes.

Claims

1. A semiconductor device comprising:

a dielectric substrate formed on a metal carrier;

a semiconductor chip formed on the dielectric substrate and having a first electrode;

a microstrip line formed on the dielectric substrate and having a second electrode with a narrow portion and with a connecting portion having a width which is wider than that of the narrow portion, the connecting portion to be connected to the first electrode; and

wires, having different lengths, for connecting the first and second electrodes,

wherein each length of the wires is determined to reduce phase difference of current flowing between the first electrode and the narrow portion of the second electrode by the wires.

2. The semiconductor device according to claim 1, wherein the second electrode has a side which faces the semiconductor chip and the side is arc-shaped and each of the wires has one end connected to the second electrode and each one end is located at a same distance from the side.

3. The semiconductor device according to claim 2, wherein each length of the wires is determined based on a distance between the microstrip line and the one end thereof.

4. The semiconductor device according to claim 1, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

5. A semiconductor device comprising:

a metal carrier;

a dielectric substrate formed on said metal carrier;

a semiconductor chip formed on said metal carrier and having a first electrode;

a microstrip line formed on the dielectric substrate and having a second electrode with a narrow portion and with a connecting portion having a width which is wider than that of the narrow portion, the connecting portion to be connected to the first electrode; and

wires, having different lengths, for connecting the first and second electrodes, each length of the wires is determined to reduce phase difference of current flowing between the first electrode and the narrow portion of the second electrode by the wires.

6. The semiconductor device according to claim 5, wherein the second electrode has a side which faces the semiconductor chip and the side is arc-shaped and each of the wires has one end connected to the second electrode and each one end is located at a same distance from the side.

7. The semiconductor device according to claim 6, wherein each length of the wires is determined based on a distance between the microstrip line and the one end thereof.

8. The semiconductor device according to claim 5, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

9. A semiconductor device comprising:

a dielectric substrate formed on a metal carrier;

a semiconductor chip formed on the dielectric substrate and having a first electrode; and

a microstrip line formed on the dielectric substrate and having a second electrode which is divided into a plurality of electrode patterns to be electrically connected to the first electrode,

wherein the plurality of electrode patterns have different widths which become smaller from most outer ones of the plurality of electrode patterns toward a central one of the plurality of electrode patterns, and each of the widths is determined to reduce phase difference of current flowing between the first electrode and the second electrode by the plurality of the electrode patterns.

10. The semiconductor device according to claim 9, wherein the second electrode has a width greater than that of the microstrip line.

11. The semiconductor device according to claim 9, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

12. A semiconductor device comprising:

a dielectric substrate formed on a metal carrier;

a semiconductor chip formed on the dielectric substrate and having a first electrode; and

a microstrip line formed on the dielectric substrate and having a second electrode which is divided into a plurality of electrode patterns to be electrically connected to the first electrode,

wherein the plurality of electrode patterns have different impedances which become higher from most outer ones of the plurality of electrode patterns toward a central one of the plurality of electrode patterns, and the impedances of the plurality of electrode patterns are determined so as to reduce phase difference of current flowing between the first electrode and the second electrode by the plurality of the electrode patterns.

13. The semiconductor device according to claim 12, wherein the second electrode has a width greater than that of the microstrip line.

14. The semiconductor device according to claim 12, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

15. A semiconductor device comprising a metal carrier;

a dielectric substrate formed on said metal carrier;

a semiconductor chip formed on said dielectric substrate and in contact with said metal carrier and having a first electrode; and

a microstrip line formed on the dielectric substrate and having a second electrode which is divided into a plurality of electrode patterns to be electrically connected to the first electrode,

wherein the plurality of electrode patterns have different widths which become smaller from most outer ones of the plurality of electrode patterns toward a central one of the plurality of electrode patterns, and each of the widths is determined to reduce phase difference of current flowing between the first electrode and the second electrode by the plurality of the electrode patterns.

16. The semiconductor device according to claim 15, wherein the second electrode has a width greater than that of the microstrip line.

17. The semiconductor device according to claim 15, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

18. A semiconductor device comprising:

a metal carrier;

dielectric substrate formed on said metal carrier;

a semiconductor chip formed in contact with said metal carrier and having a first electrode; and

a microstrip line formed on the dielectric substrate and having a second electrode which is divided into a plurality of electrode patterns to be electrically connected to the first electrode,

wherein the plurality of electrode patterns have different impedances which become higher from most outer ones of the plurality of electrode patterns toward a central one of the plurality of electrode patterns, and the impedances of the plurality of electrode patterns are determined to reduce phase difference of current flowing between the first electrode and the second electrode by the plurality of electrode patterns.

19. The semiconductor device according to claim 18, wherein the second electrode has a width greater than that of the microstrip line.

20. The semiconductor device according to claim 18, wherein a via hole filled with a metal is formed in the dielectric substrate and the semiconductor chip is connected to the metal carrier through the via hole.

21. A monolithic integrated circuit comprising:

a semiconductor chip formed on a dielectric substrate and having a first electrode; and

a microstrip line formed on the dielectric substrate and having a second electrode which is divided into a plurality of electrode patterns to be electrically connected to the first electrode,

wherein the plurality of electrode patterns hare different widths which become smaller from most outer ones of the plurality of electrode patterns toward a central one of the plurality of electrode patterns, and each of the widths is determined to reduce phase difference of current flowing between the first electrode and the second electrode by the plurality of the electrode patterns.

22. The semiconductor device according to claim 21, wherein the second electrode has a width greater than that of the microstrip line.