Core cell structure and corresponding process for NAND-type high performance flash memory device
DC CAFCFirst Claim
1. A NAND-type flash memory device, comprising:
- a core region comprising a stacked gate flash memory cell structure and a select gate transistor; and
a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer,wherein a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same, and a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same.
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Accused Products
Abstract
A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.
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Citations
7 Claims
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1. A NAND-type flash memory device, comprising:
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a core region comprising a stacked gate flash memory cell structure and a select gate transistor; and a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer, wherein a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same, and a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A NAND-type flash memory device, comprising:
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a core region comprising a stacked gate flash memory cell structure having a thin oxide material forming a tunnel oxide layer, a first conductive material forming a poly1 layer overlying the tunnel oxide layer, an insulating material forming an insulating layer overlying the poly1 layer and a second conductive material forming a poly2 layer overlying the insulating layer; the core region further comprising a select gate transistor having a gate oxide material forming a gate oxide layer and the second conductive material forming a gate layer overlying the gate oxide layer; and a periphery region including a low voltage transistor and a high voltage transistor, wherein the same gate oxide formation step used to form the gate oxide layer of the select gate transistor also forms a gate oxide laver of the low voltage transistor and thus a thickness of the gate oxide layers of the select gate transistor and the low voltage transistor are substantially the same.
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Specification