Positive/negative high voltage charge pump system

• US 6,023,188 A
• Filed: 01/15/1999
• Issued: 02/08/2000
• Est. Priority Date: 11/05/1996
• Status: Expired due to Term

• Current Assignee: Secure Axcess LLC (Prism Technologies Group, Inc.)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Tsao, Hsing-Ya, Lee, Peter W., Hsu, Fu-Chang
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/232,115
• Time in Patent Office: 389 Days
• Field of Search: 327/534, 327/535, 327/536, 327/537, 307/110
• US Class Current: 327/536
• CPC Class Codes: G05F 3/20 using diode- transistor combinations G05F3/18 takes precedence
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A two-phase high voltage generator circuit is electronically reconfigurable to output positive (V_Pp) or negative (V_Pn) high voltage, depending upon whether positive or negative mode operation is selected. The circuit includes a plurality of series-connected charge multiplier stages that each comprises a MOS transistor and a charging capacitor. Collectively the stages define an anode node and a cathode node. One of two non-overlapping phase signals is coupled to the free end of each charging capacitor such that adjacent charging capacitors are driven by different phases. First and second two-way multiplexers (MUX1, MUX2) control voltages presented to the anode and cathode nodes, to determine whether circuit operation is positive or negative mode. The MOS devices may be PMOS or NMOS, and preferably Vt-cancellation is provided for each charging stage. A precharge/discharge circuit preferably is coupled to each voltage node including the load capacitor. Further, substrate-well protection is provided such that the MOS devices are less prone to exhibit voltage breakdown or substrate to source/drain current flow.

Claims

1. A high voltage charge pump operable from low voltage Vdd and electronically reconfigurable to output from an output port a positive high voltage V_Pp in a positive mode, or a negative high voltage V_Pn in a negative mode, comprising:

a semiconductor substrate;

a charge pump circuit, fabricated on said substrate, having an anode node and a cathode node and including a number (N) of series-coupled charge pump stages, each of said stages including a MOS transistor and being AC-coupled to receive one of two non-overlapping phase pulse train signals of amplitude E1, where E1≦

Vdd, such that adjacent said stages receive different ones of said phase pulse train signals;

said pump stages multiplying the AC-coupled E1 amplitude pulse train signals to create a larger magnitude potential therefrom; and

a switching mechanism, fabricated on said substrate, coupled to said charge pump circuit;

wherein when said charge pump circuit is to operate in said positive mode, said switching mechanism couples a source of said Vdd to said anode node, couples said cathode node to said output port to deliver said V_Pp, and couples a substrate node of each said MOS transistor to a first potential;

said larger magnitude potential created by said charge pump circuit having magnitude V_Pp ; and

wherein when said charge pump circuit is to operate in said negative mode, said switching mechanism couples a negative potential to said cathode node, couples said anode node to said output port to deliver said V_Pn, and couples a substrate node of each said MOS transistor to a second potential;

said larger magnitude potential created by said charge pump circuit having magnitude V_Pnp.

2. The high voltage charge pump of claim 1, wherein said substrate is P-type material, and each said transistor is a PMOS transistor fabricated in an N-well fabricated in said substrate.

3. The high voltage charge pump of claim 1, wherein said substrate is P-type material, and each said transistor is an NMOS transistor fabricated in a P-well fabricated in an N-well fabricated in said substrate.

4. The high voltage charge pump of claim 1, wherein each said transistor is configured as a diode.

5. The high voltage charge pump of claim 1, wherein said switching mechanism includes a first two-way multiplexer unit (MUX1) and a second two-way multiplexer unit (MUX2);

wherein;

said anode node is coupled to an output node of MUX1, and said cathode node is coupled to an output node of MUX2;

a first input node of MUX1 and a first input node of MUX2 are each coupled to Vdd in positive mode and are coupled to ground in negative mode; and

a second input node of MUX1 and a second input node of MUX2 are each coupled to said output port to output said V_Pp in positive mode, and to output said V_Pn in negative mode.

6. The high voltage charge pump of claim 1, wherein said switching mechanism precharges said output port to a potential approximating (Vdd-Vt) in positive mode, and to a potential approximating Vt in negative mode, where Vt is threshold voltage for said MOS transistor.

7. The high voltage charge pump of claim 1, wherein:

said substrate is P-type material, and each said transistor is a PMOS transistor fabricated in an N-well fabricated in said substrate; and

said switching mechanism includes a first two-way multiplexer unit (MUX1) and a second two-way multiplexer unit (MUX2);

wherein said anode node is coupled to an output node of MUX1, and said cathode node is coupled to an output node of MUX2;

a first input node of MUX1 and a first input node of MUX2 are each coupled to receive Vdd in positive mode and ground in negative mode;

a second input node of MUX1 and a second input node of MUX2 are each coupled to said output port to output said V_Pp in positive mode, and to output said V_Pn in negative mode;

and further including bias means. coupled to said N-well, for changing N-well potential as a function of positive mode or negative mode operation of said high voltage charge pump to protect said PMOS transistor against breakdown.

8. The high voltage charge pump of claim 1, wherein:

said substrate is P-type material, and each said transistor is an NMOS transistor fabricated in a P-well fabricated in an N-well fabricated in said substrate; and

said switching mechanism includes a first two-way multiplexer unit (MUX1) and a second two-way multiplexer unit (MUX2);

wherein said anode node is coupled to an output node of MUX1, and said cathode node is coupled to an output node of MUX2;

a first input node of MUX1 and a first input node of MUX2 are each coupled to receive Vdd in positive mode and ground in negative mode; and

a second input node of MUX1 and a second input node of MUX2 are each coupled to said output port to output said V_Pp in positive mode, and to output said V_Pn in negative mode.

9. A high voltage charge pump system, fabricated on a semiconductor substrate, operable from low voltage Vdd and electronically reconfigurable to output from an output port a positive high voltage V_Pp in a positive mode, or a negative high voltage V_Pn in a negative mode, the system comprising:

a charge pump circuit, fabricated on said substrate, having an anode node and a cathode node and including a plurality of series-coupled solid-state charge pump MOS transistors AC-coupled to receive one of two pulse train signals of amplitude E1≦

Vdd and to output a larger magnitude potential therefrom;

a switch mechanism, fabricated on said substrate, coupled to said charge pump transistors;

a bias circuit, fabricated on said substrate, coupled to said solid-state charge pump transistors so as to vary at least one of a substrate bias voltage and a well bias voltage thereof as a function of positive mode or negative mode operation of said system;

wherein when said system is to operate in said positive mode, said switch mechanism couples a source of said Vdd to said anode node, and couples said cathode node to said output port to deliver said V_Pp ;

said larger magnitude potential created by said charge pump circuit having a magnitude of said V_Pp ; and

wherein when said system is to operate in said negative mode, said switch mechanism couples a negative potential to said cathode node, and couples said anode node to said output port to deliver said V_Pn, said larger magnitude potential created by said charge pump circuit having a magnitude of said V_Pn.

10. The system of claim 9, wherein said solid state charge pump transistors are selected from a group consisting of (a) a PMOS transistor, (b) an NMOS transistor, and (c) a MOS transistor configured as a diode.

11. The system of claim 9, wherein said switch mechanism includes a first two-way multiplexer unit (MUX1) and a second two-way multiplexer unit (MUX2);

wherein said anode node is coupled to an output node of MUX1, and said cathode node is coupled to an output node of MUX2;

a first input node of MUX1 and a first input node of MUX2 are together coupled to Vdd in positive mode and coupled to ground in negative mode; and

wherein a second input node of MUX1 and a second input node of MUX2 are together coupled to said output port to output said V_Pp in positive mode, and to output said V_Pn in negative mode.

12. The system of claim 9, wherein said substrate is P-type material, and each of said solid-state charge pump transistors is a PMOS transistor fabricated in an N-well fabricated in said substrate.

13. The system of claim 12, wherein bias voltage varied by said bias circuit is potential at said N-well.

14. The system of claim 9, wherein said substrate is P-type material, and each of said solid-state charge pump transistors is an NMOS transistor fabricated in a P-well fabricated in an N-well in said substrate.

15. The system of claim 11, wherein at least one of said MUX1 and said MUX2 comprises a PMOS transistor series-coupled to an NMOS transistor.

16. The system of claim 9, wherein:

said substrate is P-type material, each of said solid state charge pump transistors is a PMOS transistor fabricated in an N-well fabricated in said substrate;

said switch mechanism includes a first two-way multiplexer unit (MUX1) and a second two-way multiplexer unit (MUX2), at least one of said MUX1 and MUX2 comprising a series-coupled PMOS transistor and an NMOS transistor;

wherein said anode node is coupled to an output node of MUX1, and said cathode node is coupled to an output node of MUX2;

a first input node of MUX1 and a first input node of MUX2 are together coupled to Vdd in positive mode and to ground in negative mode;

a second input node of MUX1 and a second input node of MUX2 are together coupled to said output port to output said V_Pp in positive mode, and to output said V_Pn in negative mode; and

wherein said bias circuit varies bias potential at said N-well as a function of positive mode or negative mode operation of said system.

17. The system of claim 9, further including a phase generator, fabricated on said substrate, outputting said pulse train signals.

18. The system of claim 14, wherein bias voltage varied by said bias circuit is potential at said P-well.

19. A method of multiplying a low voltage Vdd in an electronically reconfigurable system whose output port provides a positive high voltage V_Pp in positive mode, or a negative high voltage V_Pn in negative mode, the method comprising the following steps:

providing a charge pump having an anode node and a cathode node and receiving AC-coupled pulse train signals of amplitude E1≦

Vdd and multiplving said pulse train signals to create a larger magnitude potential therefrom;

said charge pump including a plurality of series-coupled pump stages, each of said stages including a MOS transistor;

coupling a switchably reconfigurable switching mechanism to said charge pump such that;

when said charge pump is to operate in said positive mode, said switching mechanism coupling a source of said Vdd to said anode node, and coupling said cathode node to said output port to deliver said V_Pp ;

said larger magnitude potential created by said charge pump having magnitude V_Pp ; and

when said pump is to operate in said negative mode, said switching mechanism coupling a negative potential to said cathode node, and coupling said anode node to said output port to deliver said V_Pn ;

said larger magnitude potential created by said charge pump having magnitude V_Pnp ; and

coupling a substrate or well node of each said MOS transistor to a first potential when said pump operates in said positive mode, and coupling said substrate or well node of each said MOS transistor to a second potential when said pump operates in said negative mode.

20. The method of claim 19, wherein each said MOS transistor in said charge pump is a PMOS transistor fabricated in an N-well fabricated on a P-type semiconductor substrate upon which said switching mechanism is also fabricated;

and wherein said node is coupled to said N-well such that N-well potential is varied as a function of positive mode or negative mode of said charge pump.