Method for changing the weight of a synaptic element
First Claim
1. In an array of N-channel MOS transistors formed in a p-type substrate, said N-channel MOS transistors each including a drain electrode, a source electrode, a control gate and a floating gate on which electrons may be stored to establish a floating gate potential, said array arranged in rows and columns and having a unique row line associated with each row of said array and a unique column line associated with each column of said array, said source electrodes of all of said N-channel MOS transistors in a row connected to said unique row line associated with that row and said drain electrodes of all of said N-channel MOS transistors in a column are connected to said unique column line associated with said column, a method for selectively decreasing said floating gate potential of a selected one of one of said N-channel MOS transistors comprising the steps of:
- injecting minority electrons into said substrate;
applying a positive potential of at least 3.2 volts to the one of said row lines and the one of said column lines associated with said selected one of said N-channel MOS transistors while simultaneously maintaining all other ones of said row and column lines at voltages less than less than about 1.5 volts.
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Accused Products
Abstract
An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array. Each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. A current-sum line is associated with each of the columns in the array. Each current-sum line is connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. Circuitry is provided for forward biasing said p-well with respect to the substrate. Circuitry is provided for simultaneously driving a selected one of the bias lines low while driving a selected one of the tunnel lines high, for raising the floating gate voltage of the one of the N-channel MOS transistors common to the selected one of the bias lines and the selected one of the tunnel lines.
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Citations
11 Claims
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1. In an array of N-channel MOS transistors formed in a p-type substrate, said N-channel MOS transistors each including a drain electrode, a source electrode, a control gate and a floating gate on which electrons may be stored to establish a floating gate potential, said array arranged in rows and columns and having a unique row line associated with each row of said array and a unique column line associated with each column of said array, said source electrodes of all of said N-channel MOS transistors in a row connected to said unique row line associated with that row and said drain electrodes of all of said N-channel MOS transistors in a column are connected to said unique column line associated with said column, a method for selectively decreasing said floating gate potential of a selected one of one of said N-channel MOS transistors comprising the steps of:
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injecting minority electrons into said substrate; applying a positive potential of at least 3.2 volts to the one of said row lines and the one of said column lines associated with said selected one of said N-channel MOS transistors while simultaneously maintaining all other ones of said row and column lines at voltages less than less than about 1.5 volts.
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2. A method of increasing a weight value associated with a synaptic element with a synaptic array, said synaptic element including an N-channel MOS transistor having a floating gate having a tunneling junction with a tunneling electrode, a source, and a drain, said method comprising:
removing electrons from the synaptic element by driving the floating gate to a negative power-supply rail voltage used by the synaptic array and driving the tunneling electrode to a positive potential sufficient to induce electron tunneling in the synaptic element. - View Dependent Claims (3)
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4. A method of increasing a weight value associated with a synaptic element, said method comprising:
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driving a first gate line to a negative power-supply rail voltage used by a synaptic array; driving a first tunneling line to a positive voltage potential sufficient to induce electron tunneling in the synaptic element; driving a second gate line to a positive power-supply rail voltage used by said synaptic array; driving a second tunneling line to a voltage potential which is insufficient to induce electron tunneling in a second N-channel MOS transistor having a tunneling electrode coupled to said second tunneling line; wherein the synaptic element is comprised of a first N-channel MOS transistor having a floating gate coupled to said first gate line, a tunneling electrode coupled to said first tunneling line, a source and a drain; and wherein said synaptic array includes a third N-channel MOS transistor having a floating gate coupled to said second gate line, and a tunneling electrode coupled to said first tunneling line. - View Dependent Claims (5, 6)
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7. A method of decreasing a weight value associated with a synaptic element, said method comprising:
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injecting electrons to the synaptic element by driving a source and a drain which are associated with the synaptic element to a positive potential sufficient to induce electron injection, wherein the synaptic element is comprised of an N-channel MOS transistor having said source, said drain, a floating gate and a tunneling electrode, the synaptic element associated with a set synaptic elements that each have a source, a drain, a floating gate, and a tunneling electrode, the synaptic element and said set of synaptic elements forming an array of synaptic elements; and driving low said source and said drain corresponding to each of said set of synaptic elements. - View Dependent Claims (8)
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9. A method of decreasing a weight value associated with a synaptic element, said method comprising:
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driving a first row line and a first column-sum line to said positive voltage potential; driving a second row line and a second column-sum line to a voltage potential less than said positive voltage potential; and wherein the synaptic element is comprised of a first N-channel MOS transistor having a source coupled to said first row line, a drain coupled to said first column-sum line, a floating gate and a tunneling electrode, the synaptic element associated with a synaptic array, said synaptic array having a second N-channel MOS transistor having a source coupled to said second row line, a drain coupled to said second column-sum line, a tunneling electrode, and a floating gate. - View Dependent Claims (10, 11)
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Specification