Nonvolatile memory system, semiconductor memory, and writing method

• US 6,023,425 A
• Filed: 06/29/1999
• Issued: 02/08/2000
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/342,231
• Time in Patent Office: 224 Days
• Field of Search: 365/185.24, 365/185.18, 365/185.21, 365/185.22, 365/185.28, 365/185.29
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. In a nonvolatile semiconductor memory device comprising:

a plurality of memory cells each of which has a threshold voltage corresponding to data of one of a write state and an erase state;

a plurality of word lines each of which is coupled with corresponding memory cells of said plurality of memory cells; and

a controller controlling a predetermined operation in response to a command supplied thereto,

wherein said controller controls an erase operation to erase data of selected memory cells coupled to a word line when an erase command is supplied to said controller,

wherein said controller controls a write operation to write data to a memory cell of said memory cells coupled to said word line when a write command is supplied to said controller,

wherein said controller controls an additional write operation to write data to a memory cell which is a memory cells of said erase state in a word line coupled with memory cells being said write and said erase state when an additional write command is supplied to said controller,

wherein, in said erase operation, threshold voltages of memory cells coupled to a word line are allocated to said erase state by using a tunnel phenomenon, and

wherein, in said write and said additional write operation, a threshold voltage of a memory cell is allocated to said write state by using a tunnel phenomenon.

2. A nonvolatile semiconductor memory device according to claim 1, further comprising a circuit which forms a write expected value data based on data read from memory cells coupled to a selected word line and additional write data supplied from outside.

3. A nonvolatile semiconductor memory device according to claim 2, further comprising a data register which stores data to be written to a memory cell coupled to a selected word line,

wherein, in said additional write operation, said data register stores said write expected value data.

4. A nonvolatile semiconductor memory device according to claim 3, further comprising a plurality of data lines each of which coupled with corresponding memory cells,

wherein said data register is coupled to said plurality of data lines.

5. A nonvolatile semiconductor memory device according to claim 4, wherein each of said plurality of memory cells has a floating gate.