Method for configuring circuits over a data communications link

• US 6,023,565 A
• Filed: 02/24/1997
• Issued: 02/08/2000
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wells, Robert W., Lawman, Gary R., Linoff, Joseph D.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/805,378
• Time in Patent Office: 1,079 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500, 395/200.5, 395/500.02, 395/500.17, 395/500.18, 395/500.19, 395/200.61
• US Class Current: 716/102
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.

Claims

1. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said netlist being compiled from a design file in accordance with parameters selected by a user, said design file comprising a parameter selection, the method comprising the following steps:

a) on a first computer, displaying said parameter selection on a screen display in table-based format;

b) on said first computer, receiving a selection of parameters from a user, said parameters being specified by the user based on said screen display;

c) on said first computer, entering said parameters in said design file, thereby configuring said design file in accordance with said parameters;

d) transmitting said design file from said first computer to a second computer over a data communications link;

e) remotely compiling on said second computer, said design file to generate said netlist; and

f) transmitting said netlist from said second computer to said first computer over said data communications link.

2. The method recited in claim 1 wherein said data communications link comprises a Wide Area Network.

3. The method recited in claim 1 wherein said data communications link comprises a Local Area Network (LAN).

4. The method recited in claim 1 wherein said data communications link comprises first and second transducers forming links to each of said first and second computers, respectively.

5. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said netlist being compiled from a design file in accordance with parameters selected by a user, said design file comprising a parameter selection, the method comprising the following steps:

a) on a first computer, displaying said parameter selection on a screen display in table-based format;

b) on said first computer, receiving a selection of parameters from a user, said parameters being specified by the user based on said screen display;

c) on said first computer, entering said parameters in said design file, thereby configuring said design file in accordance with said parameters;

d) transmitting said design file from said first computer to a second computer over a data communications link;

e) remotely compiling, on said second computer, said design file to generate said netlist;

f) remotely generating, on said second computer, a schematic symbol that represents said netlist; and

g) transmitting said netlist and said schematic symbol from said second computer to said first computer over said data communications link.

6. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said netlist being compiled from a design file in accordance with parameters selected by a user, said design file comprising a parameter selection, the method comprising the following steps:

a) on a first computer, displaying said parameter selection on a screen display in table-based format;

b) on said first computer, receiving a selection of parameters from a user, said parameters being specified by the user based on said screen display;

c) on said first computer, entering said parameters in said design file, thereby configuring said design file in accordance with said parameters;

d) transmitting said design file from said first computer to a second computer over a data communications link;

e) remotely compiling, on said second computer, said design file to generate said netlist;

f) remotely generating, on said second computer, an HDL instantiation that represents said netlist; and

g) transmitting said netlist and said HDL instantiation from said second computer to said first computer over said data communications link.

7. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said netlist being compiled from a design file in accordance with parameters selected by a user, said design file comprising a parameter selection, the method comprising the following steps:

a) on a first computer, displaying said parameter selection on a screen display in table-based format;

b) on said first computer, receiving a selection of parameters from a user, said parameters being specified by the user based on said screen display;

c) on said first computer, entering said parameters in said design file, thereby configuring said design file in accordance with said parameters;

d) transmitting said design file from said first computer to a second computer over a data communications link;

e) remotely compiling, on said second computer, said design file to generate said netlist;

f) remotely placing and routing, on said second computer, said netlist to produce a placed and routed design; and

g) transmitting said placed and routed design from said second computer to said first computer over said data communications link.

8. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said netlist being compiled from a design file in accordance with parameters selected by a user, said design file comprising a parameter selection, the method comprising the following steps:

a) on a first computer, displaying said parameter selection on a screen display in table-based format;

b) on said first computer, receiving a selection of parameters from a user, said parameters being specified by the user based on said screen display;

c) on said first computer, entering said parameters in said design file, thereby configuring said design file in accordance with said parameters;

d) transmitting said design file from said first computer to a second computer over a data communications link;

e) remotely compiling on said second computer, said design file to generate said netlist;

f) remotely placing and routing, on said second computer, said netlist to produce a placed and routed design;

g) remotely generating, on said second computer, a device program file from said placed and routed design; and

h) transmitting said device program file from said second computer to said first computer over said data communications link.

9. A method for off loading work from a computer while generating a netlist representing a circuit for a programmable IC, said programmable IC having at least one bit-storage space, said netlist being compiled from a design file including data to be stored in said bit storage space, said bit-storage space being represented by a memory map, the method comprising the following steps:

a) on a first computer, displaying said memory map on a screen display in table-based format;

b) on said first computer, receiving said data specified by the user to be stored in said bit-storage space based on said screen display;

c) on said first computer, entering said data in said design file;

d) transmitting said design file from said first computer to a second computer over a data communications link; and

e) remotely compiling, on said second computer, said design file to generate said netlist.

10. The method recited in claim 9 wherein said data is specified using toggle buttons.

11. The method recited in claim 9 wherein said data is specified using pull-down menus.

12. The method recited in claim 9 wherein said data is specified using keyboard entry.

13. The method recited in claim 9 wherein said data is specified in an alpha-numeric format other than binary.

14. The method recited in claim 9 wherein said circuit comprises a PCI bus compatible interface circuit.

15. The method recited in claim 14 wherein at least a portion of said bit-storage space represents a PCI base address register.

16. The method recited in claim 14 wherein at least a portion of said bit-storage space represents a PCI configuration space header.

17. The method recited in claim 9 wherein said data communications link is bidirectional, and further comprising the step of:

f) transmitting said netlist from said second computer to said first computer over said data communications link.

18. The method recited in claim 9 wherein said data communications link comprises a Wide Area Network.

19. The method recited in claim 9 wherein said data communications link comprises a Local Area Network (LAN).

20. The method recited in claim 9 wherein said data communications link comprises first and second transducers forming links to each of said first and second computers, respectively.

21. The method recited in claim 9 wherein said data communications link is bidirectional, and further comprising the steps of:

f) remotely generating, on said second computer, a schematic symbol that represents said netlist; and

g) transmitting said netlist and said schematic symbol from said second computer to said first computer over said data communications link.

22. The method recited in claim 9 wherein said data communications link is bidirectional, and further comprising the steps of:

f) remotely generating, on said second computer, an HDL instantiation that represents said netlist; and

g) transmitting said netlist and said HDL instantiation from said second computer to said first computer over said data communications link.

23. The method recited in claim 9 wherein said data communications link is bidirectional, and further comprising the steps of:

f) remotely placing and routing, on said second computer, said netlist to produce a placed and routed design.

24. The method recited in claim 23 further comprising the step of:

g) transmitting said placed and routed design from said second computer to said first computer over said data communications link.

25. The method recited in claim 23 further comprising the steps of:

g) remotely generating, on said second computer, a device program file from said placed and routed design; and

h) transmitting said device program file from said second computer to said first computer over said data communications link.

26. A method for off loading work from a computer while compiling a logic circuit to be implemented in a programmable integrated circuit (IC), the method comprising the steps of:

a) entering, on a first computer, data descriptive of the logic circuit;

b) transmitting the data from the first computer to a second computer over a wide area data communications network;

c) remotely compiling the data on the second computer to generate a netlist corresponding to the logic circuit; and

d) transmitting the netlist from the second computer to the first computer over the network.

27. A method for off loading work from a computer while compiling a logic circuit to be implemented in a programmable integrated circuit (IC), the method comprising the steps of:

a) entering, on a first computer, data descriptive of the logic circuit;

b) transmitting the data from the first computer to a second computer over a wide area data communications network;

c) remotely compiling the data on the second computer to generate a netlist corresponding to the logic circuit; and

d) remotely generating on the second computer, from the netlist, a bitstream for programming at least a portion of the programmable IC.

28. The method of claim 27, further comprising the step of:

e) transmitting the bitstream from the second computer to the first computer over the rework.

29. A method for off loading work from a computer while compiling a logic circuit to be implemented in a programmable integrated circuit (IC), the method comprising the steps of:

a) entering, on a first computer, data descriptive of the logic circuit;

b) transmitting the data from the first computer to a second computer over a wide area data communications network;

c) remotely compiling the data on the second computer to generate a netlist corresponding to the logic circuit;

d) remotely placing and routing the netlist on the second computer; and

e) transmitting the placed and routed netlist from the second computer to the first computer over the network.

30. A method for off loading work from a computer while compiling a logic circuit to be implemented in a programmable integrated circuit (IC), the method comprising the steps of:

a) entering, on a first computer, data descriptive of the logic circuit;

b) transmitting the data from the first computer to a second computer over a wide area data communications network;

c) remotely compiling the data on the second computer to generate a netlist corresponding to the logic circuit;

d) remotely placing and routing the netlist on the second computer; and

e) remotely generating a bitstream on the second computer from the placed and routed netlist.

31. The method of claim 30, further comprising the step of:

f) transmitting the bitstream from the second computer to the first computer over the network.