Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network

• US 6,023,570 A
• Filed: 02/13/1998
• Issued: 02/08/2000
• Est. Priority Date: 02/13/1998
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Chan, Albert, Tang, Howard Y. M., Tsui, Cyrus Y.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US09/023,506
• Time in Patent Office: 725 Days
• Field of Search: 395/500, 395/500.18, 395/500.02, 326/38, 326/37
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data network, a wireless data network such as an infra-red data network and a radio wave data network, or a hybrid network including both a wired data network portion and a wireless data network portion. An access interface connects the host controller to an ISP programmer over the wired or wireless communication link. The ISP programmer programs the ISP system in accordance with ISP programming conventions. The ISP programmer can be provided by an integrated circuit having a microprocessor core.

Claims

1. A system for programming multiple programmable integrated circuits, comprising:

a) an in-system programmable (ISP) system having a plurality of ISP devices;

b) a programmer communicating with said ISP system, for programming said ISP devices;

c) a controller communicating with said programmer, said controller transmitting control data and programming data to said programmer; and

d) a communication link connecting said controller to said programmer, said communication link comprising a wireless data network.

2. The system of claim 1, wherein said ISP devices receive data input signals from said programmer and said programmer receives a data output signal from said ISP devices.

3. The system of claim 1, additionally comprising more than one of said ISP system, wherein said programmer is connected to all of said ISP systems for programming said ISP systems in sequence.

4. The system of claim 1, additionally comprising more than one of said programmer and said ISP system wherein each of said programmers is connected to one of said ISP systems for programming said ISP systems simultaneously.

5. The system of claim 1, wherein said programmer comprises a central processing unit.

6. The system of claim 5, wherein said programmer additionally comprises a writeable control store coupled to said central processing unit.

7. The system of claim 6, wherein said programmer additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

8. The system of claim 5, wherein said programmer additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

9. The system of claim 5, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

10. The system of claim 6, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

11. The system of claim 7, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

12. The system of claim 8, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

13. The system of claim 5, wherein said programmer additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

14. The system of claim 11, wherein said programmer additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

15. The system of claim 1, wherein said programmer additionally comprises a driver for transporting data input signals.

16. The system of claim 14, wherein said programmer additionally comprises a driver for transporting said data input signals.

17. The system of claim 1, wherein said controller comprises a host central processing unit.

18. The system of claim 1, additionally comprising a storage element from which said controller retrieves said programming data.

19. The system of claim 1, wherein said communication link additionally comprises a wired data network communicating with said wireless data network.

20. The system of claim 1, wherein said wireless data network comprises a transmitter for converting electrical pulses to radio wave signals and a corresponding receiver for converting said radio wave signals back to said electrical pulses.

21. The system of claim 1, wherein said wireless data network comprises a transmitter for converting electrical pulses to infra-red signals and a corresponding receiver for converting said infra-red signal back to said electrical pulses.

22. A system for programming multiple programmable integrated circuits, comprising:

a) an in-system programmable (ISP) system having a plurality of ISP devices;

b) programming means communicating with said ISP system for programming said ISP devices;

c) controller means communicating with said programming means for transmitting control data and programming data to said programming means; and

d) interface means for connecting said controller means to said programming means through a communication means, wherein said communication means is a wireless data network.

23. The system of claim 22, wherein said ISP devices receive data input signals from said programming means and said programming means receives a data output signal from said ISP devices.

24. The system of claim 22, additionally comprising more than one of said ISP system wherein said programming means programs said ISP systems in sequence.

25. The system of claim 22, additionally comprising more than one of said ISP system wherein said programming means comprises a plurality of programmers, each connected to one of said ISP systems, said programming means programs said ISP systems simultaneously.

26. The system of claim 22, wherein said programming means comprises a central processing unit.

27. The system of claim 26, wherein said programming means additionally comprises a writeable control store coupled to said central processing unit.

28. The system of claim 27, wherein said programming means additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

29. The system of claim 26, wherein said programming means additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

30. The system of claim 26, wherein said programming means additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

31. The system of claim 27, wherein said programming means additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

32. The system of claim 28, wherein said programming means additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

33. The system of claim 29, wherein said programming means additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

34. The system of claim 26, wherein said programming means additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

35. The system of claim 32, wherein said programming means additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

36. The system of claim 22, wherein said programming means additionally comprises a driver for transporting data input signals.

37. The system of claim 35, wherein said programming means additionally comprises a driver for transporting said data input signals.

38. The system of claim 22, wherein said controller means comprises a host central processing unit.

39. The system of claim 22, additionally comprising a storage means from which said controller means retrieves said programming data.

40. The system of claim 22, wherein said communication means additionally comprises a a wired data network communicating with said wireless data network.

41. The system of claim 22, wherein said wireless data network comprises transmitting means for converting electrical pulses to radio wave signals and corresponding receiving means for converting said radio wave signals back to said electrical pulses.

42. The system of claim 22, wherein said wireless data network comprises transmitting means for converting electrical pulses to infra-red signals and corresponding receiving means for converting said infra-red signals back to said electrical pulses.

43. A method for programming multiple programmable integrated circuits, comprising the acts of:

a) providing a controller;

b) connecting said controller to a programmer through a communicating link, said communication link comprises a wireless data network;

c) transmitting, through said communication link, programming data and control data from said controller to said programmer; and

d) programming a plurality of in-system programmable (ISP) systems using said programmer.

44. The method of claim 43, wherein said communication link additionally comprises a wired data network communicating with said wireless data network.

45. The method of claim 43, wherein said wireless data network comprises a transmitter for covering electrical pulses to radio wave signals and a corresponding receiver for converting said radio wave signals back to said electrical pulses.

46. The method of claim 43, wherein said wireless data network comprises a transmitter for covering electrical pulses to infra-red signals and a corresponding receiver for converting said infra-red signals back to said electrical pulses.

47. The method of claim 43, wherein said programmer programs said ISP systems in sequence.

48. The method of claim 43, additionally comprising connecting said controller to a plurality of said programmers wherein each of said programmers is communicating with one of said ISP systems for programming said ISP systems simultaneously.

49. The method of claim 43, wherein said programmer comprises a central processing unit.

50. The method of claim 49, wherein said programmer additionally comprises a writeable control store coupled to said central processing unit.

51. The method of claim 50, wherein said programmer additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

52. The method of claim 49, wherein said programmer additionally comprises a random access memory coupled to said central processing unit for allowing said programming data to be stored therewith and retrieved therefrom.

53. The method of claim 49, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

54. The method of claim 50, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

55. The method of claim 51, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

56. The method of claim 52, wherein said programmer additionally comprises an input clocked memory element coupled to said central processing unit for holding data input signals.

57. The method of claim 49, wherein said programmer additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

58. The method of claim 55, wherein said programmer additionally comprises an output clocked memory element coupled to said central processing unit for holding a data output signal.

59. The method of claim 43, wherein said programmer additionally comprises a driver for transporting data input signals.

60. The method of claim 58, wherein said programmer additionally comprises a driver for transporting said data input signals.

61. The method of claim 43, additionally comprising retrieving, prior to act (c), said programming data by said controller from a storage element.

62. The method of claim 43, additionally comprising indicating, subsequent to act (d), programming results of said ISP systems.

63. A method for programming multiple programmable integrated circuits, comprising the acts of:

a) providing a controller;

b) transmitting programming data and control data from said controller to a programmer; and

c) programming a plurality of in-system programmable (ISP) systems using said programmer;

wherein said programming act comprises providing data input signals to said ISP systems and receiving data output signals from said ISP systems, said ISP system containing a plurality of daisy-chained ISP devices.

64. A system for programming multiple programmable integrated circuits, comprising:

(a) an in-system programmable (ISP) system having an ISP device;

(b) a programmer communicating with said ISP system to program said ISP device, said programmer having a central processing unit, a writeable control store, a random access memory, an input clocked memory element, and an output clocked memory element; and

(c) a controller transmitting data to said programmer through a communication link.

65. The system of claim 64, wherein said programmer additionally comprises a driver.

66. The system of claim 64, wherein said communication link comprises a wired data network.

67. The system of claim 64, wherein said communication link comprises a wireless data network.

68. The system of claim 67, wherein said wireless data network is operated by a transmission of radio wave signals.

69. The system of claim 67, wherein said wireless data network is operated by a transmission of infra-red signals.