Power consumption reduction in medical devices employing multiple digital signal processors

• US 6,023,641 A
• Filed: 10/28/1998
• Issued: 02/08/2000
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): EVANISKO, GEORGE ROBERT
• Application Number:
  US09/181,460
• Time in Patent Office: 468 Days
• Field of Search: 607/1, 607/2, 607/4, 607/5, 607/9, 607/16
• US Class Current: 607/9
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power consumption in medical devices is reduced through the use and operation of multiple digital signal processing systems. Each processor of the multiple systems performs at least one particular function in a predetermined time period. The multiple digital signal processors of such systems can be operated at lower clock frequencies relative to those that would be required by one of such processors to complete the multiple functions within the predetermined time period. With reduced clock frequency, power consumption is reduced. Further, with reduced clock speed, supply voltages applied to such digital signal processors may also be reduced.

Claims

1. A medical device, comprising:

a first digital signal processing system for receiving data of at least a first analog input, the first digital signal processing system including a first digital signal processor operating on the data representative of the at least first analog input to perform at least a first function during a predetermined time period;

a second digital signal processing system for receiving data of at least a second analog input, the second digital signal processing system including a second digital signal processor operating on the data representative of the at least second analog input to perform at least a second function during the predetermined time period; and

a supply voltage source operatively connected to provide a first supply voltage to the first digital signal processor and a second supply voltage to the second digital signal processor, wherein the first and second supply voltages are such that the power consumed by the first and second digital signal processors in performance of the first and second functions in the predetermined time period is less than the power that would be consumed if only one of the first and second digital signal processors were to perform both of the first and second functions within the predetermined time period.

2. The device of claim 1, wherein the device further includes a clock circuit for providing a first and second clock frequency to control operation of the first and second digital signal processors during performance of the first function and the second function, respectively, and further wherein the first and second clock frequencies are such that the power consumed by the first and second digital signal processors in performance of the first and second functions during the predetermined time period is less than the power that would be consumed if only one of the first and second digital signal processors were to perform both of the first and second functions within the predetermined time period.

3. The device of claim 2, wherein the level of the first and second supply voltage are based on the first and second clock frequency, respectively.

4. The device of claim 3, wherein the first function is performed at a clock frequency about equal to the clock frequency used for performing the second function, and further wherein the first and second supply voltages are about equal.

5. The device of claim 1, wherein at least one of the first and second functions is selected from the group of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

6. The device of claim 1, wherein the device is an hermetically sealed implantable medical device.

7. The device of claim 6, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

8. The device of claim 1, wherein at least one of the first and second digital processing systems comprise circuits selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

9. A method of conserving electrical power in a medical device, the method comprising the steps of:

providing a first digital signal processor of the medical device receiving data representative of at least a first analog input;

applying a first supply voltage to the first digital signal processor for operation on the data representative of the at least first analog input to perform at least a first function during a predetermined time period;

providing a second digital signal processor of the medical device receiving data representative of at least a second analog input; and

applying a second supply voltage to the second digital signal processor for operation on the data representative of the at least second analog input to perform at least a second function during the predetermined time period,

wherein the first and second supply voltages are such that the power consumed by the first and second digital signal processors in performance of the first and second functions is less than the power that would be consumed if only one of the first and second digital signal processors were to perform both of the first and second functions within the predetermined time period.

10. The device of claim 9, wherein the method further includes operating the first and second digital signal processors at a first and second clock frequency, respectively, to control operation of the first and second digital signal processors during performance of the respective first and second functions, and further wherein the first and second clock frequencies are such that the power consumed by the first and second digital signal processors during performance of the first and second functions is less than the power that would be consumed if only one of the first and second digital signal processors were to perform both of the first and second functions within the predetermined time period.

11. The device of claim 9, wherein the level of the first and second supply voltage is based on the first and second clock frequency, respectively.

12. The device of claim 11, wherein the first clock frequency is about equal to the second clock frequency, and further wherein the first supply voltage is about equal to the second supply voltage.

13. The device of claim 9, wherein at least one of the first and second functions is selected from the group of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

14. The device of claim 9, wherein the device is an hermetically sealed implantable medical device.

15. The device of claim 14, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

16. The device of claim 9, wherein at least one of the first and second digital processing systems comprise circuits selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.