Computer with programmable arrays which are reconfigurable in response to instructions to be executed

• US 6,023,755 A
• Filed: 07/22/1998
• Issued: 02/08/2000
• Est. Priority Date: 07/29/1992
• Status: Expired due to Term

• Current Assignee: Tarofiss Data Limited Liability Company
• Original Assignee: Virtual Computer Incorporated (Cloud Software Group)
• Inventors: Casselman, Steven M.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/120,958
• Time in Patent Office: 566 Days
• Field of Search: 395/500, 395/800.36, 395/800.37, 395/800.33, 395/384, 395/570, 364/488, 364/489, 364/490, 364/491, 364/578, 340/825.83, 340/825.86, 340/825.87, 712/36, 712/37, 712/33, 712/208, 712/229
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Claims

1. A method of operating an array of plural field programmable gates (FPG'"'"'s) and a controller in order to execute a sequence of instructions, comprising:

said controller receiving information defining at least a next one of a succession of computing operations, each of said operations corresponding to at least a respective one of or a respective group of said instructions;

said controller generating, from said next one of said succession of computing operations, a set of respective logic configurations for respective ones of said plural FPGs, said set of respective logic configurations corresponding to said next one of said succession of computing operations; and

said controller re-configuring the FPGs in said array to said set of logic configurations corresponding to said next one of said succession of computing operations.

2. The method of claim 1 wherein said re-configuring step reconfigures said FPGs from a previous set of configurations corresponding to a previous one of said succession of computing operations.

3. The method of claim 2 whereby said array of FPGs is enabled to perform said succession of computing operations sequentially so as to execute said sequence of instructions.

4. The method of claim 1 wherein each of said logic configurations defines at least one of:

(a) internal logic structures of respective ones of said FPGs;

(b) connections between respective ones of said FPGs in said array and others of said FPGs in said array.

5. A method of operating a plurality of plural field programmable gates (FPG'"'"'s) in order to execute a sequence of instructions, comprising:

receiving information defining at least a next one of a succession of computing operations, each of said operations corresponding to at least a respective one of or a respective group of said instructions;

generating, from said next one of said succession of computing operations, a set of respective logic configurations for respective ones of said FPGs, said set of respective logic configurations corresponding to said next one of said succession of computing operations; and

re-configuring the FPGs in said array to said set of logic configurations coresponding to next one of said succession of computing operations.

6. The method of claim 5 wherein said re-configuring step reconfigures said FPGs from a previous set of configurations corresponding to a previous one of said succession of computing operations.

7. The method of claim 6 whereby said array of FPGs is enabled to perform said succession of computing operations sequentially so as to execute said sequence of instructions.

8. The method of claim 5 wherein each of said logic configurations define (a) internal logic structures of respective ones of said FPGs and (b) connections between respective ones of said FPGs and others of said FPGs.

9. The method of claim 5 further comprising performing said receiving, generating and re-configuring steps by at least selected ones of said FPGs.

10. The method of claim 5 further comprising dividing said plural FPGs into a control section comprising said selected ones of said FPGs by which said receiving, generating and re-configuring steps are carried out, and a re-configurable section which is re-configured by said re-configuring step.

11. The method of claim 5 further comprising providing a processor-like device and performing said receiving, generating and re-configuring steps in said processor-like device.

12. The method of claim 5 further comprising:

providing a processor-like device; and

performing at least a portion of at least one of said receiving, generating and re-configuring steps in said processor-like device.

13. The method of claim 5 further comprising:

providing a control array of FPGs; and

performing at least a portion of at least one of said receiving, generating and re-configuring steps in said control array of FPGS.