Method and apparatus for generation of test bitstreams and testing of closed loop transducers

• US 6,023,960 A
• Filed: 04/28/1999
• Issued: 02/15/2000
• Est. Priority Date: 12/17/1997
• Status: Expired due to Term

• Current Assignee: I/O Sensors Incorporated
• Original Assignee: I/O Sensors Incorporated
• Inventors: Dupuie, Scott T., Abrams, Michael L., Gannon, Jeffery C., Mayo, Franklin W., Johnson, Richard A., Jones, Ben W.
• Primary Examiner(s): RAEVIS, ROBERT R
• Application Number:
  US09/304,421
• Time in Patent Office: 293 Days
• Field of Search: 73/1.01, 73/1.37
• US Class Current: 73/1.01
• CPC Class Codes: G01P 21/00 Testing or calibrating of apparatus or devices covered by the preceding groups

Abstract

A high performance method and apparatus for testing a closed loop transducer is disclosed. A test bitstream signal is combined with a ΣΔ feedback bitstream of the transducer to produce a combined bitstream which is converted to a physical feedback to the sensor of the transducer. The ΣΔ bitstream output of the transducer is recorded for later analysis so as to test characteristics of the transducer. The test bitstream signal is preferably an oversampled, pulse density modulated signal. A testing arrangement is provided which is based upon the storage of short-length test patterns which are repetitively accessed to form a continuous test pattern. The test bitstream provided by the method of the invention produces very low noise and low distortion test signals where a repetitive test pattern is equivalent in length to one period of the test signal.

Claims

1. A method for generating a test bitstream for testing a closed loop transducer which includes a sensor and an Analog-to-Digital converter (ADC) having a Σ

Δ

bitstream which is fed back to said sensor, comprising the steps of

generating a pattern bitstream and

repeating said test pattern bitstream to form said test bitstream.

2. The method of claim 1 wherein said step of generating said pattern bitstream includes the steps of

(a) producing a simulation model of said closed loop transducers with a Σ

Δ

modulator (MUT) and providing at least one performance specification of said MUT;

(b) producing a simulation of a test pattern generating (TPG) modulator where said TPG modulator is characterized by simulation parameters;

(c) specifying said simulation of a TPG modulator with a first set of simulation parameters to produce a pattern bitstream which is short in time length compared to said test bitstream;

(d) repeating said pattern bitstream to produce a candidate test bitstream;

(e) applying said candidate test bitstream in said step of combining said test bitstream with said Σ

Δ

to produce said combined bitstream;

(f) repeating said steps (c), (d), and (e) by varying said simulation parameters until a final candidate test bitstream used in said simulation of said MUT produces stable operation which meets said at least one performance specification; and

(g) storing said final candidate test bitstream for use as said test bitstream.

3. The method of claim 2 wherein said simulation parameters of said TPG modulator are at least to a modulator high-pass cutoff frequency f_H and to a block size of said pattern bitstream and wherein said at least one performance specification of said MUT is a signal-to-quantization noise ratio SQR.