Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask

• US 6,025,273 A
• Filed: 04/06/1998
• Issued: 02/15/2000
• Est. Priority Date: 04/06/1998
• Status: Expired due to Term

• Current Assignee: TSMC China Company Limited (Taiwan Semiconductor Manufacturing Company Limited)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tao, Hun-Jan, Tsai, Chia-Shiung, Chen, Chao-Cheng
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): Vinh, Lan
• Application Number:
  US09/055,433
• Time in Patent Office: 680 Days
• Field of Search: 438/712, 438/710, 438/637, 438/624, 438/736, 134/1.2
• US Class Current: 438/706
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F⁺) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O₂ to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.

Claims

1. A method for fabricating improved contact holes in an interlevel dielectric (ILD) layer on a semiconductor substrate for integrated circuits, comprising the steps of:

providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer;

depositing said interlevel dielectric (ILD) layer on said electrically conducting layer;

depositing a polysilicon layer on said interlevel dielectric (ILD) layer;

ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer;

forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes;

anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist;

anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon atoms released from said carbon doped polysilicon layer during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said interlevel dielectric layer;

removing said photoresist layer;

annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer;

blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes;

cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching, and completing said interlevel dielectric (ILD) layer having said improved contact holes.

2. The method of claim 1, wherein the electrically conducting layer is composed of conductively doped polysilicon having a thickness of between about 2000 and 3000 Angstroms.

3. The method of claim 1, wherein said interlevel dielectric layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 6000 and 10000 Angstroms.

4. The method of claim 1, wherein said interlevel dielectric layer is silicon oxide (SiO₂) deposited by plasma enhance chemical vapor deposition using tetraethosiloxane (TEOS) as the reactant gas.

5. The method of claim 1, wherein said polysilicon layer has a thickness of between about 1000 and 2000 Angstroms.

6. The method of claim 5, wherein said polysilicon layer is ion implanted with carbon (C) at a dose of between 1.0 E 17 and 5.0 E 17 atoms/cm² and at a implant energy of between about 200 and 400 KeV.

7. The method of claim 1, wherein said openings in said carbon doped polysilicon layer are etched using reactive ion etching (RIE) and an etchant gas mixture composed of chlorine and hydrogen bromide.

8. The method of claim 1, wherein said contact holes in said interlevel dielectric layer are etched using a high density plasma (HDP) etcher and an etchant gas mixture composed of at least one of the group consisting of CF₄, CHF₃, C₂ F₆, and C₄ F8.

9. The method of claim 1, wherein said annealing is carried out in an oxygen ambient at a temperature of at least 800 degrees centigrade.

10. The method of claim 1, wherein any said residual carbon atoms are removed from the surface of said silicon oxide using a solution of sulfuric acid (H₂ SO₄) and hydrogen peroxide (H₂ O₂).

11. A method for fabricating an interlevel dielectric (ILD) layer having improved metal plug contacts on a semiconductor substrate for integrated circuits, comprising the steps of:

providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer;

depositing said interlevel dielectric (ILD) layer on said electrically conducting layer;

depositing a polysilicon layer on said interlevel dielectric (ILD) layer;

ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer;

forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes;

anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist;

anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon released from said carbon doped polysilicon layer, during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said insulating layer;

removing said photoresist layer;

annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer;

blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes;

cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching;

depositing a barrier layer over and in said contact openings;

forming metal plug contacts in said contact openings.

12. The method of claim 11, wherein the electrically conducting layer is composed of conductively doped polysilicon having a thickness of between about 2000 and 3000 Angstroms.

13. The method of claim 11, wherein said interlevel dielectric layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 6000 and 10000 Angstroms.

14. The method of claim 11, wherein said interlevel dielectric layer is silicon oxide (SiO₂) deposited by plasma enhanced chemical vapor deposition (PECVD) using tetraethosiloxane as the reactant gas.

15. The method of claim 11, wherein said polysilicon layer has a thickness of between about 1000 and 2000 Angstroms.

16. The method of claim 15, wherein said polysilicon layer is ion implanted with carbon (C) at a dose of between 1.0 E 17 and 5.0 E 17 atoms/cm² and at a implant energy of between about 200 and 400 KeV.

17. The method of claim 11, wherein said openings in said carbon doped polysilicon layer are etched using reactive ion etching (RIE) and an etchant gas mixture composed of chlorine and hydrogen bromide.

18. The method of claim 11, wherein said contact holes in said interlevel dielectric layer are etched using a high density plasma (HDP) etcher and an etchant gas mixture composed of at least one of the group consisting of CF₄, CHF₃, C₂ F₆, and C₄ F8.

19. The method of claim 11, wherein said annealing is carried out in an oxygen ambient at a temperature of at least 800 degrees centigrade.

20. The method of claim 11, wherein any said residual carbon atoms are removed from the surface of said silicon oxide using a solution of sulfuric acid (H₂ SO₄) and hydrogen peroxide (H₂ O₂).

21. The method of claim 11, wherein said barrier layer is titanium nitride (TiN) and has a thickness of between about 400 and 900 Angstroms.

22. The method of claim 11, wherein said metal plug contacts are composed of tungsten (W) and are formed by depositing a tungsten film sufficient to fill the contact holes and is then blanket etched back to the silicon oxide layer.