Apparatus for equalizing signal parameters in flip chip redistribution layers

• US 6,025,647 A
• Filed: 11/24/1997
• Issued: 02/15/2000
• Est. Priority Date: 11/24/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Wheeler, Richard L., Shenoy, Jayarama N.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/976,564
• Time in Patent Office: 813 Days
• Field of Search: 257/775, 257/773, 257/203, 257/208, 257/778
• US Class Current: 257/775
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance

Abstract

Disclosed is a redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device and a method for making the same. The redistribution layer includes a plurality of slot pads arranged along a periphery of the redistribution layer. The plurality of slot pads are formed from the patterned metallization layer. An array of bump pads are arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads are formed from the patterned metallization layer. The redistribution layer further includes a plurality of traces that are formed from the patterned metallization layer and are configured to interconnect the plurality of slot pads to the array of bump pads. Each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces. Additionally, each trace may include a bump pad area and possibly capacitance extending stubs that may be custom sized to substantially equalize a capacitance parameter associated with each of the plurality of traces.

Claims

1. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device, comprising:

a plurality of slot pads arranged along a periphery of the redistribution layer, the plurality of slot pads being formed from the patterned metallization layer;

an array of bump pads being arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads being formed from the patterned metallization layer, wherein each bump pad of the array of bump pads has a surface area that is selected to substantially equalize a capacitance parameter associated with an interconnection between a first selected one of the plurality of slot pads and a first bump pad of the array of bump pads; and

a plurality of traces formed from the patterned metallization layer being configured to interconnect the plurality of slot pads to the array of bump pads, such that each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces.

2. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein a shorter length of a first trace of the plurality of traces has a thinner width relative to a longer length of a second trace of the plurality of traces.

3. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein the capacitance parameter is equalized with respect to a selected adjacent interconnection between a second selected one of the plurality of slot pads and a second bump pad of the array of bump pads.

4. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 3, further including a capacitance extending stub that is connected to a selected one of the plurality of traces, an area of the capacitance extending stub being sized to equalize the capacitance parameter for the selected one of the plurality of traces.

5. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 4, wherein the capacitance extending stub has a notch and a stub resistance, the notch being configured to prevent the resistance parameter associated with the selected one of the plurality of traces from substantially decreasing in response to the stub resistance.

6. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein at least one of the plurality of bump pads has a notch and an associated bump pad resistance, and the notch is configured to prevent the resistance parameter associated with a selected one of the plurality of traces from substantially decreasing in response to the bump pad resistance.

7. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein the redistribution layer is formed over a lower dielectric layer, and the lower dielectric layer is formed over a lower patterned metallization layer that is coupled to a ground.

8. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 7, wherein a lumped capacitor has a upper plate that is formed from the redistribution layer, a lower plate that is formed from the lower patterned metallization layer, and the lower dielectric layer that lies between the redistribution layer and the lower patterned metallization layer.

9. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 8, wherein the upper plate of the lumped capacitor includes a first bump pad of the plurality of bump pads, a first trace of the plurality of the traces that is connected to the first bump pad, and a first slot pad of the plurality of slot pads that is connected to the first trace, such that a lower capacitance area of the lower plate is configured to be at least as large as the surface area of the first bump pad.

10. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, further including an additional power and ground routing area arranged in a center of the redistribution layer such that the array of bump pads surround the additional power and ground routing area.

11. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein the array of bump pads are arranged throughout the redistribution layer.

12. A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device as recited in claim 1, wherein each one of the array of bump pads has a pitch of about 200 μ

m between each of an adjacent bump pad.

13. A redistribution layer formed from a patterned metallization layer, comprising:

a plurality of slot pads arranged along a periphery of the redistribution layer, the plurality of slot pads being formed from the patterned metallization layer, wherein a first slot pad has a first slot pad capacitance value and a second slot pad has a second slot pad capacitance value;

an array of bump pads being arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads being formed from the patterned metallization layer, wherein a first bump pad of the array of bump pads has a first surface area having a first bump pad capacitance value and a second bump pad of the array of bump pads has a second surface area having a second bump pad capacitance value;

a plurality of traces having a plurality of widths formed from the patterned metallization layer being configured to interconnect the plurality of slot pads to the array of bump pads, wherein a first trace that electrically connects the first bump pad to the first slot pad has a first trace capacitance and a first length, and a second trace that electrically connects the second bump pad to the second slot pad has a second trace capacitance value and a second length, the first length being different than the second length, and

wherein the first surface area of the first bump pad is sized such that the first bump pad capacitance value, plus the first trace capacitance value, plus the first slot pad capacitance value substantially equals the second bump pad capacitance value, plus the second trace capacitance value, plus the second slot pad capacitance value.

14. A redistribution layer formed from a patterned metallization layer as recited in claim 13, wherein the first surface area of the first bump pad is greater than the second surface area of the second bump pad, and the first length is shorter than the second length.

15. A redistribution layer formed from a patterned metallization layer as recited in claim 13, wherein the first trace includes a first width and a first resistance value, and the second trace includes a second width and a second resistance value, the first width and the second width are selected so that the first resistance value substantially equals the second resistance value.

16. A redistribution layer formed from a patterned metallization layer as recited in claim 15, wherein the first trace has a capacitance extending stub that is sized such that the first bump pad capacitance value plus the first trace capacitance value plus the first slot pad capacitance value substantially equals the second bump pad capacitance value plus the second trace capacitance value plus the second slot pad capacitance value.

17. A redistribution layer formed from a patterned metallization layer as recited in claim 15, wherein the first width is narrower than the second width, and the first length of the first trace is shorter than the second length of the second trace.

18. A redistribution layer formed from a patterned metallization layer as recited in claim 17, wherein the first trace has a capacitance extending stub that is sized such that the first bump pad capacitance value plus the first trace capacitance value plus the first slot pad capacitance value substantially equals the second bump pad capacitance value plus the second trace capacitance value plus the second slot pad capacitance value.

19. A redistribution layer formed from a patterned metallization layer as recited in claim 13, wherein the first trace has a capacitance extending stub that is sized such that the first bump pad capacitance value plus the first trace capacitance value plus the first slot pad capacitance value substantially equals the second bump pad capacitance value plus the second trace capacitance value plus the second slot pad capacitance value.

20. A redistribution layer formed from a patterned metallization layer as recited in claim 19, wherein the first length of the first trace is shorter than the second length of the second trace.

21. A redistribution layer formed from a patterned metallization layer as recited in claim 17, wherein the first width of the first trace is about 10 μ

m.

22. A redistribution layer formed from a patterned metallization layer as recited in claim 21, wherein the second width of the second trace is between about 25 μ

m and 30 μ

m.

23. A redistribution layer formed from a patterned metallization layer as recited in claim 22, wherein the first surface area of the first bump pad is about 280 μ

m by about 90 μ

m.

24. A redistribution layer formed from a patterned metallization layer as recited in claim 13, wherein the first surface area of the first bump pad is sized so as to minimize skew between a first signal that is output from the first bump pad and a second signal that is output from second bump pad.

25. A redistribution layer formed from a patterned metallization layer as recited in claim 15, wherein the first width of the first trace is selected so as to control skew between a first signal that is output from the first bump pad and a second signal that is output from second bump pad, and the first surface area of the first bump pad is sized so as to minimize skew between a first signal that is output from the first bump pad and a second signal that is output from second bump pad.

26. A redistribution layer formed from a patterned metallization layer as recited in claim 25, wherein the first width of the first trace is selected so as to control coupled noise between the first signal and second signal.

27. A redistribution layer formed from a patterned metallization layer as recited in claim 13, wherein the redistribution layer is formed on an integrated circuit that is a flip chip device.

28. A redistribution layer formed from a patterned metallization layer as recited in claim 27, wherein the flip chip device is attached to a PC board having traces that interconnect to a second flip chip device having the redistribution layer.

29. A redistribution layer formed from a patterned metallization layer, comprising:

a plurality of slot pads arranged along a periphery of the redistribution layer, the plurality of slot pads being formed from the patterned metallization layer, wherein a first slot pad has a first slot pad capacitance value and a second slot pad has a second slot pad capacitance value;

an array of bump pads being arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads being formed from the patterned metallization layer, wherein a first bump pad of the array of bump pads has a first surface area having a first bump pad capacitance value and a second bump pad of the array of bump pads has a second surface area having a second bump pad capacitance value;

a plurality of traces having a plurality of widths formed from the patterned metallization layer being configured to interconnect the plurality of slot pads to the array of bump pads, wherein a first trace that electrically connects the first bump pad to the first slot pad has a first trace capacitance and a first length, and a second trace that electrically connects the second bump pad to the second slot pad has a second trace capacitance value and a second length, the first length being different than the second length; and

a capacitance extending stub located on the first trace, and

wherein an area of the capacitance extending stub and the first surface area of the first bump pad are sized such that the first bump pad capacitance value, plus the first trace capacitance value, plus the first slot pad capacitance value substantially equals the second bump pad capacitance value, plus the second trace capacitance value, plus the second slot pad capacitance value.

30. A redistribution layer formed from a patterned metallization layer as recited in claim 29, wherein the first width is narrower than the second width, and the first length of the first trace is shorter than the second length of the second trace.