Glitch free delay line multiplexing technique

• US 6,025,744 A
• Filed: 04/17/1998
• Issued: 02/15/2000
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ferraiolo, Frank D., Weinstein, Samuel K., Bertolet, Allan R., Chu, Albert M.
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/062,415
• Time in Patent Office: 669 Days
• Field of Search: 327/231, 327/233, 327/235, 327/237, 327/250, 327/251, 327/261, 327/269, 327/270, 327/271, 327/276, 327/277, 327/284, 327/291, 327/299
• US Class Current: 327/276
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A glitch free delay line multiplexing technique is described that includes an intermediate multiplexing system and an output multiplexer. The intermediate multiplexing system receives signals from a plurality of delay units and outputs a subset of delay signals that includes the signal presently selected, the signal presently selected with an additional delay, and the signal presently selected with one less delay. The intermediate multiplexing system receives a control word from a select mechanism in a non-time critical manner. The output multiplexer receives the least significant bits of the control word and outputs the selected signal.

Claims

1. A glitch free delay line system comprising:

a clock signal;

a variable delay line comprising a plurality of sequentially coupled delay units, wherein the delay line comprises M output nodes and each of the M output nodes reproduces the clock signal with a varying amount of delay;

a select mechanism for choosing a predetermined amount of delay n, and for generating a selection signal in response thereto;

an M-to-N multiplexor having;

M inputs for receiving each of the delayed clock signals from the M output nodes,

a select input for receiving the selection signal from the select mechanism, and

N output lines, wherein 3<

N<

M, and wherein three of the N output lines provide clock signals having delays of n, n-1, and n+1; and

an N-to-1 multiplexor having;

N inputs coupled to the N output lines of the M-to-N multiplexor,

a select input for receiving the selection signal from the select mechanism, and

an output line, wherein the output line outputs the clock signal with n delay.

2. The system of claim 1 wherein the N output lines further provide a signal having a delay of "don'"'"'t care."

3. The system of claim 1 wherein the select mechanism is synchronized with the clock signal.

4. The system of claim 1 wherein N equals four.

5. The system of claim 1 wherein the select input of the N-to-1 multiplexor receives only a portion of the selection signal.

6. The system of claim 1 wherein the M-to-N multiplexor includes combinatorial logic for choosing the appropriate M output nodes based on the selection signal in order to provide the three clock signals having delays of n, n-1, and n+1.

7. A glitchless delay line circuit, comprising:

delay means for generating a plurality of delayed clock signals;

selection means for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n;

filter means for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and

output means for receiving the subset of delayed clock signals and for generating the clock signal having n delay.

8. The circuit of claim 7 wherein the selection means comprises:

means for delivering a first signal to the filter means; and

means for delivering a second signal to the output means,

wherein the second signal comprises a portion of the first signal.

9. The circuit of claim 8 wherein the second signal reaches the output means before the subset reaches the output means.

10. A delay lock loop comprising:

a phase detection system; and

a variable delay line, comprising;

a plurality of delay units for generating a plurality of delayed clock signals, wherein each has a varying amount of delay;

a selection mechanism for selecting the clock signal having n delay;

a filter mechanism for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and

an output mechanism for receiving the subset of delayed clock signals and for generating the clock signal having n delay.

11. The delay lock loop of claim 10 wherein the selection mechanism delivers a control word to the filter mechanism and delivers a portion of the control word to the output mechanism.

12. The delay lock loop of claim 11 wherein the portion of the control word affects the output mechanism before the subset affects the output mechanism.

13. A delay line circuit, comprising:

a delay system for generating a plurality of delayed clock signals;

a selection system for selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n;

a filter system for generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and

an output system for receiving the subset of delayed clock signals and for generating the clock signal having n delay.

14. The circuit of claim 13 wherein the selection system comprises:

a system for delivering a first signal to the filter system; and

a system for delivering a second signal to the output means, wherein the second signal comprises a portion of the first signal.

15. The circuit of claim 14 wherein the second signal reaches the output system before the subset reaches the output system.

16. A method for generating a glitch free delayed clock signal, comprising the steps of:

generating a plurality of delayed clock signals;

selecting one of the plurality of delayed clock signals, the selected clock signal having a delay of n;

generating a subset of delayed clock signals, wherein the subset includes clock signals having delays of n, n+1 and n-1; and

receiving the subset of delayed clock signals and generating the clock signal having n delay.