Integrated graphics subsystem with message-passing architecture

• US 6,025,853 A
• Filed: 03/24/1995
• Issued: 02/15/2000
• Est. Priority Date: 03/24/1995
• Status: Expired due to Term

• Current Assignee: ZiiLabs Inc., Ltd. (Creative Technology Ltd.)
• Original Assignee: 3DLabs Incorporated Limited (Creative Technology Ltd.)
• Inventors: Baldwin, David Robert
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/410,345
• Time in Patent Office: 1,789 Days
• Field of Search: 395/162-164, 395/122, 395/130, 395/131, 395/134, 395/140-143, 345/185, 345/189, 345/501, 345/505, 345/506, 345/509, 345/521, 345/522, 345/511, 345/519
• US Class Current: 345/506
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

Claims

1. A graphics processing subsystem, comprising:

at least four functionally distinct processing units, each including hardware elements which are customized to perform a rendering operation which is not performed by at least some others of said processing units;

at least some ones of said processing units being connected to operate asynchronously to one another;

a frame buffer, connected to be accessed by at least one of said processing units;

said processing units being mutually interconnected in a pipeline relationship, such that said processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture;

wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; and

wherein said processing units include a memory access unit which reads and writes a local buffer memory.

2. The graphics processing subsystem of claim 1, wherein at least some ones of said processing units include internally paralleled data paths.

3. The graphics processing subsystem of claim 1, wherein all of said processing units are integrated into a single integrated circuit.

4. The graphics processing subsystem of claim 1, wherein all of said processing units, but not said frame buffer, are integrated into a single integrated circuit.

5. The graphics processing subsystem of claim 1, further comprising a color lookup-table and analog conversion circuit which is connected to receive data from said frame buffer and to provide corresponding analog color outputs.

6. A graphics processing subsystem, comprising:

an input buffer;

a rasterizer, connected to read messages from said input buffer and to generate a sequence of pixel locations accordingly;

one or more differential data analyzers, operatively connected to receive messages from said rasterizer, and connected to provide a sequence of incrementally changing parameter values for sequences of pixel locations defined by messages received from said rasterizer;

a plurality of additional processing units, operatively connected in series in a pipeline relationship, and jointly operatively connected to receive messages from said differential data analyzers;

plural ones of said additional processing units each having customized hardware which is different from one another and from said color differential data analyzers;

said processing units being mutually interconnected in a pipeline relationship, such that individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units;

whereby said plural processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture.

7. The graphics processing subsystem of claim 6, wherein said parameter is a color value.

9. The graphics processing subsystem of claim 9, wherein said processing units include a texturing unit.

8. The graphics processing subsystem of claim 9, wherein said parameter is a depth value.

10. A graphics processing subsystem, comprising:

an input buffer;

a rasterizer, connected to read messages from said input buffer and to generate a sequence of pixel locations accordingly;

one or more differential data analyzers, operatively connected to receive messages from said rasterizer, and connected to provide a sequence of incrementally changing parameter values for sequences of pixel locations defined by messages received from said rasterizer;

a plurality of additional processing units, operatively connected in series in a pipeline relationship, and jointly operatively connected to receive messages from said differential data analyzers;

plural ones of said additional processing units each having customized hardware which is different from one another and from said color differential data analyzers;

said processing units being mutually interconnected in a pipeline relationship, such that individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units;

whereby said plural processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture; and

wherein said processing units include a memory access unit which reads and writes a local buffer memory.

11. The graphics processing subsystem of claim 10, wherein at least some ones of said processing units include internally paralleled data paths.

12. The graphics processing subsystem of claim 10, wherein said rasterizer and said differential data analyzers and all of said additional processing units are integrated into a single integrated circuit.

13. The graphics processing subsystem of claim 10, wherein said rasterizer generates step messages which are passed through all of said processors.

14. A graphics processing integrated circuit, comprising:

at least four functionally distinct processing units, each including hardware elements which are customized to perform a rendering operation which is not performed by at least some others of said processing units;

at least one of said processing units providing a frame buffer interface;

said processing units being mutually interconnected in a pipeline relationship, such that said processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture;

said processing units, but not said frame buffer, all being integrated together on a single integrated circuit;

wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; and

wherein said processing units include a memory access unit which provides a read/writes interface to a local buffer memory which is not part of said integrated circuit.

15. The graphics processing integrated circuit of claim 14, wherein at least some ones of said processing units include internally paralleled data paths.

16. A computer graphics system comprising:

a rendering subsystem which includes;

first, second, third, and fourth functionally distinct processing units, all connected to operate asynchronously to one another, and each including hardware elements which are customized to perform a rendering operation which is not performed by others of said processing units;

said processing units of said rendering subsystem being mutually interconnected in a pipeline relationship, such that said processing units jointly provide a pipelinedmultiple-instruction-multiple-device (MIMD) graphics processing architecture;

a frame buffer, connected to be accessed by at least one of said processing units of said rendering system, and accessible to provide video output; and

at least one upstream processor, connected to send data for rendering to said rendering subsystem;

wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; and

wherein said processing units include a memory access unit which reads and writes a local buffer memory.

17. The graphics system of claim 16, wherein at least some ones of said processing units include internally paralleled data paths.

18. The graphics system of claim 16, wherein all of said processing units, but not said frame buffer, are integrated into a single integrated circuit.

19. A method for rendering 3D graphics, comprising the steps of:

providing data to be rendered to a multiprocessor rendering system which includes at least four functionally distinct processing units connected in a pipeline relationship;

allocating individual rendering operations to respective ones of said processing units, and performing said rendering operations;

writing data generated by said processing units into a frame buffer, and outputting data from said frame buffer at video rates;

wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units.