Electronic memory device, in particular for use in implantable medical appliances

• US 6,026,008 A
• Filed: 06/03/1998
• Issued: 02/15/2000
• Est. Priority Date: 06/07/1997
• Status: Expired due to Term

• Current Assignee: Biotronik Mess-Und Therapiegeraete GmbH & Company Ingenieurbuero Berlin (Biotronik SE & Company KG)
• Original Assignee: Biotronik Mess-Und Therapiegeraete GmbH & Company Ingenieurbuero Berlin (Biotronik SE & Company KG)
• Inventors: Feese, Ulrich
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/089,449
• Time in Patent Office: 622 Days
• Field of Search: 365/51, 365/52, 365/63, 361/760, 361/761, 257/690, 257/691
• US Class Current: 365/63
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]

Abstract

An electronic memory device, in particular for use in implantable medical appliances, is provided with one or more electronic read/write memory chips, a carrier for the mechanical fixing of the RAM chip or chips, address inputs, a read/write input and a data bus connection, the RAM chip or chips in the memory device each being provided with two interfaces which are arranged on the input side and output side relative to the respective RAM chip and each comprise address bus, data bus and read/write connection, the address bus, data bus and read/write connection of the input-side interface being connected internally directly to the respectively allocated address bus, data bus and read/write connection of the output-side interface for signal transmission by the RAM chip.

Claims

1. An electronic memory device, in particular for use in implantable medical appliances comprising one at least electronic read/write memory chip (RAM chips) (2), a carrier (3) for mechanical fixing of the at least one RAM chip (2), address inputs (4), a read/write input (5), and a data bus connection (6), wherein the at least one RAM chip (2) in the memory device is provided with two interfaces (12,17) arranged on an input side and output side relative to the respective RAM chip (2) and each comprises address bus, data bus and read/write connection (14,15,16,18,19,20), the address bus, data bus and read/write connection (14,15,16) of the input side interface (12) being connected internally to a respectively allocated address bus, data bus and read/write connection (18,19,20) of the output side interface (17) for signal transmission through the RAM chip (2);

wherein each RAM chip (2) is provided with an address expansion arrangement (21) with input connection (22), address logic (23) and output connection (24) in which in each case a binary input value is input via the input connection (22) and on the one hand is compared by an address logic (23) with a set value for activation of the RAM chip (2) and, on the other hand, the binary input value is converted according to a predetermined algorithm into a binary output value which is present at an output connection (24) for transmission as input value to an address expansion arrangement (21) of a following RAM chip (2).

2. A memory device according to claim 1, wherein, when a plurality of RAM chips (2.1, 2.2, 2.3, 2.4) is arranged in a memory device (1), the input-side interface (12) of the first RAM chip (2.1) is coupled to associated address and read/write inputs (4, 5) and the data bus connection (6) of the memory device (1) via a chip-substrate connecting line (30).

3. A memory device according to claim 2, wherein the input-side interfaces (12) of the second and further RAM chips (2.1, 2.2, 2.3, 2.4) are coupled to the output-side interfaces (17) of a respective preceding RAM chip (2.1, 2.2, 2.3, 2.4) in the manner of a cascade via direct chip-chip connecting lines (32).

4. A memory device according to claim 1, wherein the address logic (23) comprises a binary decremental counter (26) for converting the input value.

5. A memory device according to claim 1, wherein the RAM chips (2) are arranged in modular fashion on a carrier (31) which is preferably free from connecting faces.

6. A memory device according to claim 5, comprising one of a component or housing area (31) of the appliance accommodating the memory arrangement (1) as carrier for the RAM chips (2.1, 2.2, 2.3, 2.4).

7. A memory device according to claim 1, wherein a plurality of RAM chips (2) is stacked congruently in the memory device.