Non-volatile, static random access memory with store disturb immunity
First Claim
1. A non-volatile, static random access memory (nvSRAM) with immunity to a store disturb phenomena in which a manufacturing defect can corrupt or render unstable the bit of data resident in the static random access memory (SRAM) portion of the nvSRAM and in some cases, the bit of data resident in the non-volatile (nv) portion of the nvSRAM during the store operation, the non-volatile static random access memory comprising:
- a memory cell comprising;
a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;
wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;
a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;
wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by store operation;
wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;
an interface for receiving signals relating to the store and recall operations;
a controller for issuing store and recall operation related signals to said interface of said memory cell;
wherein said controller is capable of issuing signals during a store operation to address a store disturb problem.
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Accused Products
Abstract
The invention relates to a non-volatile, static random access memory (nvSRAM) device that addresses the consequence of a manufacturing defect that occasionally occurs during mass production of the nvSRAM device and if not addressed, reduces the yield of the production process. The consequence of the defect is termed a store disturb because the execution of a store operation in a defective nvSRAM causes the bit of data retained in the SRAM portion and, in some cases, the nv portion of the nvSRAM to be instable or corrupted. The present invention provides an nvSRAM device in which the controller provides modified signals to the nvSRAM memory portion of the device that address the store disturb phenomena and, as a consequence, improve the yield of the manufacturing process.
52 Citations
20 Claims
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1. A non-volatile, static random access memory (nvSRAM) with immunity to a store disturb phenomena in which a manufacturing defect can corrupt or render unstable the bit of data resident in the static random access memory (SRAM) portion of the nvSRAM and in some cases, the bit of data resident in the non-volatile (nv) portion of the nvSRAM during the store operation, the non-volatile static random access memory comprising:
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a memory cell comprising; a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment; wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory; a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell; wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by store operation; wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation; an interface for receiving signals relating to the store and recall operations; a controller for issuing store and recall operation related signals to said interface of said memory cell; wherein said controller is capable of issuing signals during a store operation to address a store disturb problem. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for operating a non-volatile, static random access memory (nvSRAM) to compensate for a store disturb phenomena in which a manufacturing defect can corrupt or render unstable a bit of data resident in the static random access memory portion of the nvSRAM and in some cases, the bit of data resident in the non-volatile portion of the nvSRAM during the store operation, said method comprising the steps of:
providing a memory cell comprising; a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment; wherein a bit of data resident in said static random access memory can be lost if power is removed from said static random access memory; a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a copy of a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell; wherein the capability of said non-volatile memory to receive said bit of data from said static random access memory constitutes a store operation; wherein the capability of said non-volatile memory to transmit said bit of data back to said static random access memory constitutes a recall operation; and an interface for receiving signals relating to the store and recall operations; and
issuing signals to said interface to address a store disturb.- View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
Specification