Two square NVRAM cell

• US 6,026,019 A
• Filed: 06/19/1998
• Issued: 02/15/2000
• Est. Priority Date: 06/19/1998
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lam, Chung H.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/100,729
• Time in Patent Office: 606 Days
• Field of Search: 365/185.08, 365/185.17, 257/296
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile random access memory (NVRAM) cell and method of fabrication thereof. Pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure are formed vertically in silicon pillars. Source devices at the bottom of the pillar selectively provide ground to one of the cells. A floating gate extends upward from the source device'"'"'s gate line. A control gate plate extending between adjacent pillars selectively provides a programming voltage to the control gate. Both the source gate and the control gate are capacitively coupled through silicon rich oxide to the floating gate. Polysilicon plugs between silicon pillars are word line gates for cells in adjacent pillars. A diffusion at the top of each pillar is a bit line contact for both cells at the pillar. Each pair of cells on a pillar are on a common bit line and a common word line. The word line, control gate and source gate line select individual cells in the pair.

Claims

1. A non-volatile random access memory (NVRAM) array of one or more pairs of NVRAM cells, each cell of said pairs of NVRAM cells comprising:

a word line select device having a first conduction terminal connected to a bit line and gated by a word line;

a floating gate device having a first conduction terminal connected to a second conduction terminal of said word line device; and

a source device having a first conduction terminal connected to a second conduction terminal of said floating gate device and gated by a source gate line, the bit line and word line being common to both cells of each said pair of NVRAM cells.

2. The NVRAM array of claim 1, wherein a first source gate control line is connected to the source gate line of a first of each of said pairs of NVRAM cells and a second source gate control line is connected to the source gate line of each of the second of said pair NVRAM cells.

3. The NVRAM array of claim 1, wherein a first control gate line is connected to a control gate of a first of each of said pairs of NVRAM cells and a second control gate line is connected to a control gate of each of the second of said pair NVRAM cells.

4. The NVRAM array of claim 2, wherein a first control gate line is connected to a control gate of a first of each of said pairs of NVRAM cells and a second control gate line is connected to a control gate of each of the second of said pair NVRAM cells.

5. The NVRAM array of claim 1, wherein in each cell of said pair of NVRAM cells the floating gate is capacitively coupled to the cell'"'"'s source gate line.

6. A non-volatile random access memory (NVRAM) array of a plurality of pairs of NVRAM cells, each of said pairs of NVRAM cells comprising:

a silicon pillar extending upward from a silicon layer;

a bit line diffusion at the top end of said pillar;

a pair of diffusions in said silicon layer on opposite sides of said silicon pillar;

a source gate extending upward along said silicon pillar from each of said diffusions;

a floating gate extending upward from each said source gate along said silicon pillar;

a control gate extending upward from each said source gate parallel and capacitively coupled to said floating gate;

a word line plug on each of said opposite sides disposed above each said control gate and along said silicon pillar between said floating gate and said bit line diffusion.

7. The NVRAM array of claim 6 further comprising silicon rich oxide between said floating gate and said source gate.

8. The NVRAM array of claim 7 further comprising silicon rich oxide between said floating gate and said control gate.

9. The NVRAM array of claim 8 wherein at least one said control gate is a plate between a pair of floating gates in adjacent said pairs of cells on adjacent said silicon pillars.

10. The NVRAM array of claim 9 wherein said word line plug is a word line gate for a word line device in each of said adjacent silicon pillars.