Semiconductor memory device

• US 6,026,029 A
• Filed: 05/29/1997
• Issued: 02/15/2000
• Est. Priority Date: 04/18/1991
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubshi Electric Engineering Company Limited (Mitsubishi Electric Corporation)
• Inventors: Saiki, Tsukasa, Abe, Hideaki, Yamazaki, Akira, Konishi, Yasuhiro, Dosaka, Katsumi, Ishizuka, Yasuhiro, Iwamoto, Hisashi, Himukashi, Katsumitsu, Hayano, Kouji, Kumanoya, Masaki
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/865,310
• Time in Patent Office: 992 Days
• Field of Search: 365/230.01, 365/189.01, 365/230.03, 365/230.06, 365/230.08
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Claims

1. A semiconductor memory device incorporating an externally applied signal in synchronization with an external clock signal having first transitions, each from a first logic level to a second logic level and second transitions, each from the second logic level to the first logic level, comprising:

an address generation circuit receiving and incorporating two or more time-division multiplexed address signals to generate internal address signals in synchronization with the external clock signal,

said address generation circuit including means responsive to an access instruction signal for being activated to latch the respective time-division multiplexed address signals in synchronization with predetermined transitions of said first transitions and said second transitions of said external clock signal for generating said internal address signals.

2. The semiconductor memory device according to claim 1, wherein the time-division multiplexed address signals include a first address signal and a second address signal, and said internal address signals include a first internal address signal and a second internal address signal, and wherein said address generation circuit includes,

a first address control means responsive to said access instruction signal and the external clock signal for generating a first address load signal on a first transition of said first transitions of the external clock signal,

a second address control means responsive to said first address load signal and the external clock signal for generating a second address load signal on a second transition subsequent to said first transition,

a first address latch means responsive to said first address load signal for latching the first address signal to generate the first internal address signal, and

a second address latch means responsive to said second address load signal for latching said second address signal to generate the second internal address signal.

3. The semiconductor memory device according to claim 1, wherein said address generation circuit includes mode select means responsive to a mode select signal for determining latching timing for latching a subsequent time-division multiplexed address signal with respect to a first applied time-division multiplexed address signal, said subsequent time-division multiplexed address signal applied subsequent to said first applied time-division address signal.

4. The semiconductor memory device according to claim 3, wherein said mode select means includes means responsive to said mode select signal for setting the timing of latching said subsequent time-division multiplexed address signal to one of a half cycle of said external clock signal later, a cycle of said external clock signal later and two cycles of said external clock signal later with respect to the latching timing on which said first applied time-division multiplexed address signal is latched.

5. A semiconductor memory device incorporating an externally applied signal in synchronization with an external clock signal having a first transition from a first logic level to a second logic level and a second transition from the second logic level to the first logic level, comprising:

an address generation circuit receiving and incorporating two or more time-division multiplexed address signals to generate internal address signals in synchronization with the external clock signal,

said address generation circuit including means responsive to an access instruction signal for being activated to latch the respective time-division multiplexed address signals in synchronization with both of said first transition and said second transition of said external clock signal for generating said internal address signals.

6. The semiconductor memory device according to claim 5, wherein the time-division multiplexed address signals include a first address signal and a second address signal, and said internal address signals include a first internal address signal and a second internal address signal, and wherein said address generation circuit includes,

a first address control means responsive to said access instructions signal and the external clock signal for generating a first address load signal on a first transition of the external clock signal,

a second address control means responsive to said first address load signal and the external clock signal for generating a second address load signal on a second transition subsequent to said first transition,

a first address latch means responsive to said first address load signal for latching the first address signal to generate the first internal address signal, and

a second address latch means responsive to said second address load signal for latching said second address signal to generate the second internal address signal.

7. The semiconductor memory device according to claim 6, wherein said address generation circuit further includes mode select means responsive to a mode select signal for varying latching timing for latching a subsequent time-division multiplexed address signal with respect to a first applied time-division multiplexed address signal, said subsequent time-division multiplexed address signal applied subsequent to said first applied time-division address signal.

8. The semiconductor memory device according to claim 7, wherein said mode select means includes means responsive to said mode select signal for setting the timing of latching said subsequent time-division multiplexed address signal to one of a half cycle of said external clock signal later, a cycle of said external clock signal later and two cycles of said external clock signal later with respect to the latching timing on which said first applied time-division multiplexed address signal is latched.