Integrated circuit memory devices having improved precharge and I/O driver characteristics and methods of operating same

• US 6,026,035 A
• Filed: 01/07/1999
• Issued: 02/15/2000
• Est. Priority Date: 02/28/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Gyu-hong
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/226,224
• Time in Patent Office: 404 Days
• Field of Search: 365/203, 365/190, 365/189.11, 365/189.05
• US Class Current: 365/190
• CPC Class Codes: G11C 2207/12 Equalization of bit lines
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

Integrated circuit memory devices include a pair of complementary input/output lines (IO and /IO), a pair of complementary data lines (DATA and /DATA) and a driver circuit which is responsive to a driver signal (PDT) and drives the pair of complementary input/output lines with complementary data from the pair of complementary data lines when the driver signal is in an enabled state (e.g., logic 1). A precharge circuit is also provided. This precharge circuit, which is responsive to a precharge control signal (PIOPR) and the driver signal (PDT), precharges the pair of complementary input/output lines IO and /IO during a precharge time interval which precedes the generation of a column select signal (CSL). The precharge time interval commences when the driver signal (PDT) and the precharge control signal (PIOPR) are in disabled and enabled states, respectively, at the same time. The precharge time interval also terminates upon transition of the driver signal (PDT) from its disabled state to an enabled state, even if the precharge control signal remains in its enabled state.

Claims

1. An integrated circuit memory device, comprising:

a pair of complementary input/output lines;

a pair of complementary data lines;

means, responsive to a driver signal, for driving said pair of complementary input/output lines with complementary data from said pair of complementary data lines when the driver signal is in an enabled state; and

means, responsive to both a precharge control signal and the driver signal, for precharging said pair of complementary input/output lines during a precharge time interval, said precharge time interval commencing when the driver signal and the precharge control signal are in disabled and enabled states, respectively, at the same time, and terminating upon transition of the driver signal from its disabled state to an enabled state even if the precharge control signal remains in its enabled state.

2. The memory device of claim 1, wherein said precharging means comprises:

an equalization circuit electrically coupled to said pair of complementary input/output lines and responsive to a pair of complementary precharge timing signals; and

a precharge timing circuit which generates the pair of complementary precharge timing signals in response to the precharge control signal and the driver signal.

3. The memory device of claim 2, wherein said equalization circuit comprises first and second field effect transistors electrically coupled in series between said pair of complementary input/output lines.

4. The memory device of claim 2, wherein said equalization circuit comprises:

first and second NMOS transistors electrically coupled in series between said pair of complementary input/output lines; and

a PMOS transistor electrically coupled across said pair of complementary input/output lines.

5. The memory device of claim 4, wherein said first and second NMOS transistors are responsive to a first one of the pair of complementary precharge timing signals;

and wherein said PMOS transistor is responsive to a second one of the pair of complementary precharge timing signals.

6. The memory device of claim 5, wherein said precharge timing circuit comprises:

a NOR gate having a first input responsive to the driver signal and a second input responsive to an inverted version of the precharge control signal; and

an inverter having an input electrically connected to an output of said NOR gate.

7. The memory device of claim 6, wherein the output of said NOR gate is electrically connected to gate electrodes of said first and second NMOS transistors;

and wherein an output of said inverter is electrically connected to a gate electrode of said PMOS transistor.

8. The memory device of claim 7, wherein said driving means comprises:

a first buffer having first and second inputs, and an output electrically connected to a first one of said pair of complementary input/output lines;

a first NOR circuit having a first input responsive to a data signal, a second input responsive to an inverted version of the driver signal and an output electrically connected to the first input of said first buffer;

a first OR circuit having a first input responsive to a complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said first buffer;

a second buffer having first and second inputs, and an output electrically connected to a second one of said pair of complementary input/output lines;

a second NOR circuit having a first input responsive to the complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the first input of said second buffer; and

a second OR circuit having a first input responsive to the data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said second buffer.

9. The memory device of claim 1, wherein said driving means comprises:

a first buffer having first and second inputs, and an output electrically connected to a first one of said pair of complementary input/output lines;

a first NOR circuit having a first input responsive to a data signal, a second input responsive to an inverted version of the driver signal and an output electrically connected to the first input of said first buffer;

a first OR circuit having a first input responsive to a complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said first buffer;

a second buffer having first and second inputs, and an output electrically connected to a second one of said pair of complementary input/output lines;

a second NOR circuit having a first input responsive to the complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the first input of said second buffer; and

a second OR circuit having a first input responsive to the data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said second buffer.

10. An integrated circuit memory device, comprising:

a pair of complementary input/output lines;

a pair of complementary data lines;

a driver circuit, responsive to a driver signal, to drive said pair of complementary input/output lines with complementary data from said pair of complementary data lines when the driver signal is in an enabled state; and

a precharge circuit, responsive to a precharge control signal and the driver signal, to precharge said pair of complementary input/output lines during a precharge time interval, said precharge time interval commencing when the driver signal and the precharge control signal are in disabled and enabled states, respectively, at the same time, and terminating upon transition of the driver signal from its disabled state to an enabled state even if the precharge control signal remains in its enabled state.

11. The memory device of claim 10, wherein said precharge circuit:

an equalization circuit electrically coupled to said pair of complementary input/output lines and responsive to a pair of complementary precharge timing signals; and

a precharge timing circuit which generates the pair of complementary precharge timing signals in response to the precharge control signal and the driver signal.

12. The memory device of claim 11, wherein said equalization circuit comprises first and second field effect transistors electrically coupled in series between said pair of complementary input/output lines.

13. The memory device of claim 11, wherein said equalization circuit comprises:

first and second NMOS transistors electrically coupled in series between said pair of complementary input/output lines; and

a PMOS transistor electrically coupled across said pair of complementary input/output lines.

14. The memory device of claim 13, wherein said first and second NMOS transistors are responsive to a first one of the pair of complementary precharge timing signals;

and wherein said PMOS transistor is responsive to a second one of the pair of complementary precharge timing signals.

15. The memory device of claim 14, wherein said precharge timing circuit comprises:

a NOR gate having a first input responsive to the driver signal and a second input responsive to an inverted version of the precharge control signal; and

an inverter having an input electrically connected to an output of said NOR gate.

16. The memory device of claim 15, wherein the output of said NOR gate is electrically connected to gate electrodes of said first and second NMOS transistors;

and wherein an output of said inverter is electrically connected to a gate electrode of said PMOS transistor.

17. The memory device of claim 16, wherein said driver circuit comprises:

a first buffer having first and second inputs, and an output electrically connected to a first one of said pair of complementary input/output lines;

a first NOR circuit having a first input responsive to a data signal, a second input responsive to an inverted version of the driver signal and an output electrically connected to the first input of said first buffer;

a first OR circuit having a first input responsive to a complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said first buffer;

a second buffer having first and second inputs, and an output electrically connected to a second one of said pair of complementary input/output lines;

a second NOR circuit having a first input responsive to the complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the first input of said second buffer; and

a second OR circuit having a first input responsive to the data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said second buffer.

18. The memory device of claim 10, wherein said driver circuit comprises:

a first buffer having first and second inputs, and an output electrically connected to a first one of said pair of complementary input/output lines;

a first NOR circuit having a first input responsive to a data signal, a second input responsive to an inverted version of the driver signal and an output electrically connected to the first input of said first buffer;

a first OR circuit having a first input responsive to a complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said first buffer;

a second buffer having first and second inputs, and an output electrically connected to a second one of said pair of complementary input/output lines;

a second NOR circuit having a first input responsive to the complementary data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the first input of said second buffer; and

a second OR circuit having a first input responsive to the data signal, a second input responsive to the inverted version of the driver signal and an output electrically connected to the second input of said second buffer.

19. A method of operating an integrated circuit memory device, comprising the steps of:

generating an enabled column select signal and an enabled precharge control signal during respective nonoverlapping time intervals;

driving a pair of complementary input/output lines with write data, in response to a driver signal which is enabled during a portion of a write time interval when the precharge control signal is also enabled; and

precharging the complementary input/output lines during another portion of the write time interval when the precharge control signal is enabled and the driver signal is disabled.