Phase locked loop (PLL) with linear parallel sampling phase detector

• US 6,026,134 A
• Filed: 06/19/1997
• Issued: 02/15/2000
• Est. Priority Date: 06/19/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Duffy, Michael L., Navabi, Mohammad J.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Liu, Shuwang
• Application Number:
  US08/878,714
• Time in Patent Office: 971 Days
• Field of Search: 375/376, 375/354, 375/374, 375/375, 331/11, 331/14, 331/25, 327/157, 327/12
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Claims

1. An apparatus for detecting the phase of an input signal relative to an output signal comprising:

a plurality of phase detector circuits each configured to receive (i) said input signal and (ii) a window signal, each phase detector circuit being further configured to generate a phase difference signal in response to said window signal, each of said phase difference signals being proportional to a phase difference between said input signal and said output signal;

means for generating said output signal in response to said phase difference signals, said output signal having a plurality of phases;

wherein each phase detector circuit operates according to at least one preselected phase of said output signal

and at least one of said phase detector circuits includes a function gate having an output terminal configured to generate a pump up signal, said function gate being connected to a first memory element and further having an enable terminal for receiving said window signal.

2. The apparatus of claim 1 wherein each phase difference signal comprises a pump up signal and a pump down signal.

3. The apparatus of claim 2 wherein, for each phase detector circuit, at least one of said pump up signal and said pump down signal has a pulsewidth that varies according to said phase difference.

4. The apparatus of claim 1 wherein at least one of said phase detector circuits includes:

means for generating a pump down signal connected to at least one of said first memory element and said function gate, said phase difference signal comprising said pump up signal and said pump down signal.

5. The apparatus of claim 4 wherein said phase detector circuit includes a logic circuit configured to generate said window signal in response to at least one preselected phase of said output signal.

6. The apparatus of claim 5 wherein each phase detector circuit includes a respective logic circuit for generating a plurality of window signals, said window signals each having a respective active state and a respective inactive state wherein said window signals are non-overlapping in said active state.

7. The apparatus of claim 6 wherein at least one of said pump up signal and said pump down signal has a variable pulsewidth.

8. The apparatus of claim 7 wherein said input signal is a data signal, and wherein said output terminal of said first D-type memory element is configured to output a sampled data signal when said window signal is active.

9. The apparatus of claim 8 wherein each phase detector circuit is configured to generate a respective sampled data signal, said apparatus further including a register for storing an n-bit data word in response to said sampled data signals where n equals the number of said plurality of phase detector circuits.

10. The apparatus of claim 1 wherein said output signal generating means includes a loop filter configured to generate a control signal varying in magnitude as a function of said phase difference signals.

11. The apparatus of claim 1 wherein said output signal generating means includes a voltage-controlled oscillator (VCO) configured to generate said plurality of phases of said output signal.

12. The apparatus of claim 11 wherein said VCO comprises a ring oscillator having a plurality of stages.

21. The apparatus according to claim 1, wherein each of said window signals are non-overlapping.

22. The apparatus of claim 1 wherein said phase memory element comprises:

a first D-type memory element having (i) an input terminal configured to receive said input signal, and (ii) an output terminal.

13. A parallel sampling phase detector apparatus comprising:

a plurality of phase detector circuits each configured to receive (i) an input signal and (ii) a window signal, said phase detector circuits being configured to generate a phase difference signal in response to said window signal, each of said phase difference signals being proportional to a phase difference between said input signal and an output signal;

a loop filter configured to generate a control signal in response to said phase difference signals; and

,

a voltage controlled oscillator (VCO) configured to generate said output signal in response to said control signal wherein said output signal has a plurality of phases;

wherein each phase detector circuit operates according to at least one preselected phase of said VCO output signal

and at least one of said phase detector circuits includes a function gate having an output terminal configured to generate a pump up signal, said function gate being connected to a first memory element and further having an enable terminal for receiving said window signal.

14. The phase detector apparatus of claim 13 wherein at least one of said phase detector circuits includes a logic circuit configured to generate said window signal in response to preselected ones of said plurality of phases of said VCO output signal.

15. The phase detector apparatus of claim 14 wherein each phase detector circuit includes a respective logic circuit for generating a plurality of said window signals, said window signals each having a respective active state and a respective inactive state wherein said window signals are non-overlapping in said active state.

16. A phase locked loop (PLL) having linear parallel sampling phase detectors comprising:

a plurality of linear phase detectors wherein each linear phase detector is configured to generate a respective phase difference signal in response to (i) an input signal end (ii) a window signal, each of said phase difference signals is proportional to a phase difference between said input signal and an output signal, said output signal having a plurality of phases wherein each phase detector operates in response to preselected ones of said phases; and

at least one of said phase detector circuits includes a function gate having an output terminal configured to generate a pump up signal, said function gate being connected to a first memory element and further having an enable terminal for receiving said window signal and,

means for generating said phases of said output signal in response to said phase difference signals.

17. A method of recovering data from an input data signal comprising the steps of:

(A) generating, for each one of a plurality of linear output phase detectors, a respective phase difference signal in response to (i) said input signal and (ii) a window signal, wherein each phase difference signal is proportional to a respective phase difference between the input data signal and an output signal

and at least one of said phase detector circuits includes a function gate having an output terminal configured to generate a pump up signal, said function gate being connected to a first memory element and further having an enable terminal for receiving said window signal;

(B) generating a plurality of phases of said output signal in response to the phase difference signals; and

,

(C) determining a plurality of bit values during respective bit periods of said input data signal in response to said phases of said output signal.

18. The method of claim 17 further including the step of:

storing said bit values during said bit periods to thereby form a parallel-bit data word.

19. The method of claim 17 wherein step (A) includes the substep of:

generating a pump up signal for each phase detector;

generating a pump down signal for each phase detector wherein at least one of said pump up and pump down signals have a pulsewidth that varies according to a respective one of said phase differences wherein said phase difference signals comprise said pump up and said pump down signals.

20. The method of claim 17 wherein step (C) includes the substeps of:

generating said window signal for each linear phase detector in response to preselected phases of said output signal, only one of said window signals being active at a time;

sampling, for each linear phase detector, the input data signal when a respective one of said window signals becomes active.