Local compilation in context within a design hierarchy

• US 6,026,226 A
• Filed: 10/27/1997
• Issued: 02/15/2000
• Est. Priority Date: 10/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Karchmer, David, Fairbanks, Brent A., Heile, Francis B., Herrmann, Alan L., Rawls, Tamlyn V.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US08/958,798
• Time in Patent Office: 841 Days
• Field of Search: 707/501
• US Class Current: 716/103
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
• CPC Class Codes: G06Q 10/10 Office automation; Time management
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management

Abstract

A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files. Starting from the root node down to the action point, the following steps are performed at each node: resolving current assignments based upon higher assignments at nodes located between the current node and the root node of said hierarchy tree, and elaborating the current node to produce a netlist. Once the action point node has been reached, then lower nodes of the hierarchy tree below the action point are elaborated down to the leaf nodes to produce a netlist for each of these lower nodes.

Claims

1. A computer-implemented method of compiling an electronic design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising the following:

identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis;

automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; and

elaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified.

2. The method of claim 1 wherein said design is provided as plurality of design source files.

3. The method of claim 1 wherein said identifying and applying involve performing the following for each node from a root node of said hierarchy tree down to said action point node where an action point is specified:

resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said design hierarchy tree such that said higher assignments are inherited by said current node, and

elaborating said current node to produce a netlist for said current node.

4. A computer-implemented method of compiling a plurality of design source files representing an electronic design, said design source files specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising:

analyzing one of said plurality of design source files to determine design entities represented in said source file;

performing the following for each node from a root node of said hierarchy tree down to a first node where an action point is specified,

resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said hierarchy tree, such that said higher assignments are inherited by said current node, and

elaborating said current node to produce a netlist for said current node;

elaborating lower nodes of said hierarchy tree from said first node where said action point is specified down to leaf nodes of said hierarchy tree located below said first node to produce a netlist for each of said lower nodes, whereby a local compile is performed at said first node where said action point is specified.

5. A method as recited in claim 4 wherein said electronic design specifies a programmable logic device and results of said local compile are used to program said programmable logic device.

6. A method as recited in claim 4 further comprising:

building an action point netlist at said first node using said netlists produced for said lower nodes;

synthesizing said action point netlist;

placing and routing said action point netlist; and

generating a binary programming file suitable for programming said electronic design.

7. A method as recited in claim 4 wherein said elaborating lower nodes of said hierarchy tree includes resolving lower assignments at each of said lower nodes based in part upon higher assignments at nodes located between said lower node and said root node of said hierarchy tree, such that said higher assignments are inherited by said lower node.

8. A method as recited in claim 4 further comprising:

analyzing each of said plurality of design source files to determine said plurality of design entities represented in said design source files; and

creating said design hierarchy tree based upon said determined plurality of design entities, such that said design hierarchy tree is used in said compilation.

9. A method as recited in claim 4 wherein said current assignments and said higher assignments include at least one of relative hierarchical assignments and parameters.

10. A method as recited in claim 4 wherein said action point is a simulation action point and said method of compiling is used for performing a simulation.

11. A method as recited in claim 4 wherein said action point is compile action point and said method of compiling is used for performing a timing analysis of said electronic design.

12. A computer-implemented method of compiling a plurality of design source files specifying a plurality of design entities representing an electronic design, said method comprising:

receiving a design hierarchy tree having a plurality of nodes, each of said nodes representing one of said design entities of said electronic design;

creating an action point at a local node located below a root node of said design hierarchy tree, said root node having associated root assignments;

resolving local assignments at said local node based in part upon said root assignments, such that at least one of said root assignments is inherited by said local assignments; and

performing a local compile from said local node using at least one of said root assignments, such that said local node is compiled within the context of said electronic design represented by said design hierarchy tree, and such that a portion of said design hierarchy tree located above said local node is not compiled.

13. A method as recited in claim 12 wherein said electronic design is a programmable logic device and said local compile is used for testing a portion of said programmable logic device.

14. A method as recited in claim 12 wherein said step of performing a local compile includes:

building an action point netlist at said local node;

synthesizing said action point netlist;

placing and routing said action point netlist; and

generating a binary programming file suitable for programming said electronic design.

15. A method as recited in claim 12 wherein said resolving local assignments at said local node includes a sub-step of resolving higher assignments at nodes located between said local node and said root node of said hierarchy tree, such that said higher assignments are inherited by said local node.

16. A method as recited in claim 12 further comprising:

analyzing each of said plurality of design source files to determine said plurality of design entities represented in said design source files; and

creating said design hierarchy tree based upon said determined plurality of design entities, such that said design hierarchy tree is used in said compilation.

17. A method as recited in claim 12 wherein said root assignments and said local assignments include at least one of relative hierarchical assignments and parameters.

18. A method as recited in claim 12 wherein said action point is a simulation action point and said method further comprises the step of:

performing a simulation from said local node.

19. A method as recited in claim 12 wherein said action point is compile action point and said method of compiling is used for performing a timing analysis of said electronic design.

20. A computer program product comprising a computer-usable medium having computer-readable program code embodied thereon for compiling a plurality of design source files representing an electronic design, said design source files specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said computer program product comprising computer-readable program code for effecting the following steps within a computer system:

analyzing one of said plurality of design source files to determine design entities represented in said source file;

performing the following steps for each node from a root node of said hierarchy tree down to a first node where an action point is specified,

resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said hierarchy tree, such that said higher assignments are inherited by said current node, and

elaborating said current node to produce a netlist for said current node;

elaborating lower nodes of said hierarchy tree from said first node where said action point is specified down to leaf nodes of said hierarchy tree located below said first node to produce a netlist for each of said lower nodes, whereby a local compile is performed at said first node where said action point is specified.

21. A computer program product as recited in claim 20 wherein said electronic design specifies a programmable logic device and results of said local compile are used to program said programmable logic device.

22. A computer program product as recited in claim 20 further comprising computer-readable program code for effecting the following:

building an action point netlist at said first node using said netlists produced for said lower nodes;

synthesizing said action point netlist;

placing and routing said action point netlist; and

generating a binary programming file suitable for programming said electronic design.

23. A computer program product as recited in claim 20 wherein said elaborating lower nodes of said hierarchy tree includes resolving lower assignments at each of said lower nodes based in part upon higher assignments at nodes located between said lower node and said root node of said hierarchy tree, such that said higher assignments are inherited by said lower node.

24. A computer program product as recited in claim 20 further comprising computer-readable program code for effecting the following:

analyzing each of said plurality of design source files to determine said plurality of design entities represented in said design source files; and

creating said design hierarchy tree based upon said determined plurality of design entities, such that said design hierarchy tree is used in said compilation.

25. A computer program product as recited in claim 20 wherein said current assignments and said higher assignments include at least one of relative hierarchical assignments and parameters.

26. A computer program product as recited in claim 20 wherein said action point is a simulation action point and said compiling is used for performing a simulation.

27. A computer program product as recited in claim 20 wherein said action point is compile action point and said compiling is used for performing a timing analysis of said electronic design.

28. A computer program product comprising a computer-usable medium having computer-readable program code embodied thereon for compiling a plurality of design source files specifying a plurality of design entities representing an electronic design, said computer program product comprising computer-readable program code for effecting the following within a computer system:

receiving a design hierarchy tree having a plurality of nodes, each of said nodes representing one of said design entities of said electronic design;

creating an action point at a local node located below a root node of said design hierarchy tree, said root node having associated root assignments;

resolving local assignments at said local node based in part upon said root assignments, such that at least one of said root assignments is inherited by said local assignments; and

performing a local compile from said local node using at least one of said root assignments, such that said local node is compiled within the context of said electronic design represented by said design hierarchy tree, and such that a portion of said design hierarchy tree located above said local node is not compiled.

29. A computer program product as recited in claim 28 wherein said electronic design is a programmable logic device and said local compile is used for testing a portion of said programmable logic device.

30. A computer program product as recited in claim 28 wherein said performing a local compile includes:

building an action point netlist at said local node;

synthesizing said action point netlist;

placing and routing said action point netlist; and

generating a binary programming file suitable for programming said electronic design.

31. A computer program product as recited in claim 28 wherein said resolving local assignments at said local node includes resolving higher assignments at nodes located between said local node and said root node of said hierarchy tree, such that said higher assignments are inherited by said local node.

32. A computer program product as recited in claim 28 further comprising computer-readable program code for effecting the following:

analyzing each of said plurality of design source files to determine said plurality of design entities represented in said design source files; and

creating said design hierarchy tree based upon said determined plurality of design entities, such that said design hierarchy tree is used in said compilation.

33. A computer program product as recited in claim 28 wherein said root assignments and said local assignments include at least one of relative hierarchical assignments and parameters.

34. A computer program product as recited in claim 28 wherein said action point is a simulation action point, said computer program product further comprising computer-readable program code for effecting the following:

performing a simulation from said local node.

35. A computer program product as recited in claim 28 wherein said action point is compile action point and said compiling is used for performing a timing analysis of said electronic design.

36. A computer-readable medium comprising computer code for compiling a design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said computer code of said computer-readable medium effecting the following:

identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis;

automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; and

elaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified.

37. A computer-readable medium as recited in claim 36 wherein said design is provided as plurality of design source files.

38. A computer-readable medium as recited in claim 36 wherein said identifying and said applying involve performing the following for each node from a root node of said hierarchy tree down to said action point node where an action point is specified:

resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said design hierarchy tree such that said higher assignments are inherited by said current node, and

elaborating said current node to produce a netlist for said current node.