Local compilation in context within a design hierarchy
First Claim
1. A computer-implemented method of compiling an electronic design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising the following:
- identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis;
automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; and
elaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified.
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Abstract
A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files. Starting from the root node down to the action point, the following steps are performed at each node: resolving current assignments based upon higher assignments at nodes located between the current node and the root node of said hierarchy tree, and elaborating the current node to produce a netlist. Once the action point node has been reached, then lower nodes of the hierarchy tree below the action point are elaborated down to the leaf nodes to produce a netlist for each of these lower nodes.
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Citations
38 Claims
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1. A computer-implemented method of compiling an electronic design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising the following:
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identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis; automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; and elaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified. - View Dependent Claims (2, 3)
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4. A computer-implemented method of compiling a plurality of design source files representing an electronic design, said design source files specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising:
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analyzing one of said plurality of design source files to determine design entities represented in said source file; performing the following for each node from a root node of said hierarchy tree down to a first node where an action point is specified, resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said hierarchy tree, such that said higher assignments are inherited by said current node, and elaborating said current node to produce a netlist for said current node; elaborating lower nodes of said hierarchy tree from said first node where said action point is specified down to leaf nodes of said hierarchy tree located below said first node to produce a netlist for each of said lower nodes, whereby a local compile is performed at said first node where said action point is specified. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11)
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12. A computer-implemented method of compiling a plurality of design source files specifying a plurality of design entities representing an electronic design, said method comprising:
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receiving a design hierarchy tree having a plurality of nodes, each of said nodes representing one of said design entities of said electronic design; creating an action point at a local node located below a root node of said design hierarchy tree, said root node having associated root assignments; resolving local assignments at said local node based in part upon said root assignments, such that at least one of said root assignments is inherited by said local assignments; and performing a local compile from said local node using at least one of said root assignments, such that said local node is compiled within the context of said electronic design represented by said design hierarchy tree, and such that a portion of said design hierarchy tree located above said local node is not compiled. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A computer program product comprising a computer-usable medium having computer-readable program code embodied thereon for compiling a plurality of design source files representing an electronic design, said design source files specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said computer program product comprising computer-readable program code for effecting the following steps within a computer system:
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analyzing one of said plurality of design source files to determine design entities represented in said source file; performing the following steps for each node from a root node of said hierarchy tree down to a first node where an action point is specified, resolving current assignments at a current node based in part upon higher assignments at nodes located between said current node and said root node of said hierarchy tree, such that said higher assignments are inherited by said current node, and elaborating said current node to produce a netlist for said current node; elaborating lower nodes of said hierarchy tree from said first node where said action point is specified down to leaf nodes of said hierarchy tree located below said first node to produce a netlist for each of said lower nodes, whereby a local compile is performed at said first node where said action point is specified. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A computer program product comprising a computer-usable medium having computer-readable program code embodied thereon for compiling a plurality of design source files specifying a plurality of design entities representing an electronic design, said computer program product comprising computer-readable program code for effecting the following within a computer system:
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receiving a design hierarchy tree having a plurality of nodes, each of said nodes representing one of said design entities of said electronic design; creating an action point at a local node located below a root node of said design hierarchy tree, said root node having associated root assignments; resolving local assignments at said local node based in part upon said root assignments, such that at least one of said root assignments is inherited by said local assignments; and performing a local compile from said local node using at least one of said root assignments, such that said local node is compiled within the context of said electronic design represented by said design hierarchy tree, and such that a portion of said design hierarchy tree located above said local node is not compiled. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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36. A computer-readable medium comprising computer code for compiling a design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said computer code of said computer-readable medium effecting the following:
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identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis; automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; and elaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified. - View Dependent Claims (37, 38)
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Specification