FPGA logic cell internal structure including pair of look-up tables
First Claim
1. A field programmable gate array (FPGA), comprising:
- a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including first and second look-up tables, each look-up table having a set of address inputs and an output, the address inputs of both look-up tables receiving signals from a common set of cell inputs, each logic cell also having an AND logic gate provided therein with a pair of gate inputs selectively connected to two cell inputs and with a gate output connected to one address input of both look-up tables, the outputs of said first and second look-up tables selectively connected to respective first and second cell outputs, each logic cell also including an output multiplexer selectively connected to a third cell output and having first and second multiplexer inputs connected to the respective first and second look-up table outputs and further having a control input selectively connected to an additional cell input.
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Abstract
A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces. Logic cells are directly connected to neighboring cells, including diagonally adjacent cells, and are also connected to local bus lines. The arrangement of express bus lines is preferably staggered in such a way that they connect to non-consecutive repeaters in an alternating manner. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.
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Citations
19 Claims
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1. A field programmable gate array (FPGA), comprising:
a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including first and second look-up tables, each look-up table having a set of address inputs and an output, the address inputs of both look-up tables receiving signals from a common set of cell inputs, each logic cell also having an AND logic gate provided therein with a pair of gate inputs selectively connected to two cell inputs and with a gate output connected to one address input of both look-up tables, the outputs of said first and second look-up tables selectively connected to respective first and second cell outputs, each logic cell also including an output multiplexer selectively connected to a third cell output and having first and second multiplexer inputs connected to the respective first and second look-up table outputs and further having a control input selectively connected to an additional cell input. - View Dependent Claims (2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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3. A field programmable gate array (FPGA), comprising:
a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including (a) a pair of look-up tables each having N address inputs and an output, where N is an integer greater than 1, the N address inputs of both look-up tables receiving signals from the same cell inputs, (b) means for dynamically selecting in response to an additional cell input an output of one of said pair of look-up tables to effectively form a combined (N+1)-input look-up table from said pair of look-up tables, (c) means for registering an output of at least one of said look-up tables, and (d) a pair of output selection means, each selection means receiving data signals from (i) the output of an N-input look-up table, (ii) the dynamically selected output of the combined (N+1)-input look-up table, and (iii) the registered output of one of said look-up tables, each selection means providing a selected one of the received data signals to a cell output. - View Dependent Claims (4, 17, 18, 19)
Specification