FPGA logic cell internal structure including pair of look-up tables

• US 6,026,227 A
• Filed: 09/24/1997
• Issued: 02/15/2000
• Est. Priority Date: 05/20/1996
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Furtek, Frederick C., Mason, Martin T., Luking, Robert B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/936,334
• Time in Patent Office: 874 Days
• Field of Search: 395/500.17, 395/500.18, 326/37, 326/39, 326/40
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces. Logic cells are directly connected to neighboring cells, including diagonally adjacent cells, and are also connected to local bus lines. The arrangement of express bus lines is preferably staggered in such a way that they connect to non-consecutive repeaters in an alternating manner. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.

Claims

1. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including first and second look-up tables, each look-up table having a set of address inputs and an output, the address inputs of both look-up tables receiving signals from a common set of cell inputs, each logic cell also having an AND logic gate provided therein with a pair of gate inputs selectively connected to two cell inputs and with a gate output connected to one address input of both look-up tables, the outputs of said first and second look-up tables selectively connected to respective first and second cell outputs, each logic cell also including an output multiplexer selectively connected to a third cell output and having first and second multiplexer inputs connected to the respective first and second look-up table outputs and further having a control input selectively connected to an additional cell input.

2. The FPGA of claim 1 wherein said cell inputs and cell outputs include direct cell-to-cell connections between diagonally adjacent logic cells, one of said two cell inputs connected to the gate inputs of said AND logic gate being one of said direct cell-to-cell connections.

5. The FPGA of claim 1 wherein one of a first set of cell inputs is selectively connectable to a first address input of both look-up tables and one of a second set of cell inputs is selectively connectable to a second address input of both look-up tables, said one address input of both look-up tables to which said AND logic gate output is connected being a third address input of both said look-up tables.

6. The FPGA of claim 5 wherein said first set of cell inputs includes direct cell-to-cell input connections from all orthogonally adjacent logic cells.

7. The FPGA of claim 6 wherein said first set of cell inputs also includes a bus input connection from a bus line adjacent to that logic cell.

8. The FPGA of claim 6 wherein said second set of cell inputs also includes direct cell-to-cell input connections from all orthogonally adjacent logic cells.

9. The FPGA of claim 5 wherein said second set of cell inputs includes direct cell-to-cell input connections from all diagonally adjacent logic cells.

10. The FPGA of claim 9 wherein said second set of cell inputs also includes a bus input connection from a bus line adjacent to that logic cell.

11. The FPGA of claim 1 wherein a first of said gate inputs is connected to an output of a first input multiplexer, said multiplexer having a first input connected to a bus input connection from a bus line adjacent to that logic cell and a second input receiving a fixed logic "1" level, said bus input connection thereby constituting one of said two cell inputs selectively connected via said multiplexer to said gate inputs of said AND logic gate.

12. The FPGA of claim 11 wherein a second of said gate inputs is connected to an output of a second input multiplexer, said second multiplexer having a first input connected to a second bus input connection from a bus line adjacent to that logic cell, a second input connected to a feedback line from a cell output of that logic cell, and a third input receiving a fixed logic "1" level, said second bus input connection thereby constituting the other of said two cell inputs selectively connected via said second multiplexer to said gate inputs of said AND logic gate.

13. The FPGA of claim 1 wherein said control input of said output multiplexer is connected to an output enable selecting multiplexer with a first input receiving a fixed logic "1" level and at least one other input receiving a dynamic output enable signal from a bus line, said dynamic signal thereby constituting said additional cell input.

14. The FPGA of claim 1 wherein said look-up tables comprise addressable static RAM memories.

15. The FPGA of claim 14 wherein said static RAM memories are loadable during an initial configuration of the FPGA and operable as read-only memories.

16. The FPGA of claim 14 wherein said static RAM memories have write enable and data input means for allowing said look-up table memories to be dynamically reprogrammed during operation of the FPGA.

3. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including

(a) a pair of look-up tables each having N address inputs and an output, where N is an integer greater than 1, the N address inputs of both look-up tables receiving signals from the same cell inputs,

(b) means for dynamically selecting in response to an additional cell input an output of one of said pair of look-up tables to effectively form a combined (N+1)-input look-up table from said pair of look-up tables,

(c) means for registering an output of at least one of said look-up tables, and

(d) a pair of output selection means, each selection means receiving data signals from (i) the output of an N-input look-up table, (ii) the dynamically selected output of the combined (N+1)-input look-up table, and (iii) the registered output of one of said look-up tables, each selection means providing a selected one of the received data signals to a cell output.

4. The FPGA of claim 3 further comprising a third output means for providing the dynamically selected output of the combined (N+1)-input look-up table to another cell output connected to a bus network.

17. The FPGA of claim 3 wherein said look-up tables comprise addressable static RAM memories.

18. The FPGA of claim 17 wherein said static RAM memories are loadable during an initial configuration of the FPGA and operable as read-only memories.

19. The FPGA of claim 17 wherein said static RAM memories have write enable and data input means for allowing said look-up table memories to be dynamically reprogrammed during operation of the FPGA.