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Method and apparatus for selecting an optimal system bus clock in a highly scalable computer system

  • US 6,026,231 A
  • Filed: 12/24/1997
  • Issued: 02/15/2000
  • Est. Priority Date: 03/31/1995
  • Status: Expired due to Term
First Claim
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1. A central processing unit (CPU) circuit board comprising a CPU and first circuitry for outputting, at system reset time, control inputs to a system bus clock selection circuit operative to select an appropriate system bus clock from a plurality of available system bus clocks at the system reset time for a system bus, wherein the control inputs include the type of CPU, and wherein the system bus clock selection circuit and the system bus being coupled to each other and elements of a computer system within which the CPU circuit board is integrated.

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