Method and apparatus for selecting an optimal system bus clock in a highly scalable computer system
First Claim
1. A central processing unit (CPU) circuit board comprising a CPU and first circuitry for outputting, at system reset time, control inputs to a system bus clock selection circuit operative to select an appropriate system bus clock from a plurality of available system bus clocks at the system reset time for a system bus, wherein the control inputs include the type of CPU, and wherein the system bus clock selection circuit and the system bus being coupled to each other and elements of a computer system within which the CPU circuit board is integrated.
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Abstract
An oscillator output selector and complementary control circuitry are provided to a computer system. The oscillator output selector is used to select a series of clock pulses for usage as system bus clock. The control circuitry controls the selection being made by the oscillator output selector, in accordance to control inputs received. In one embodiment, the control circuitry receives system bus clock frequency preferences from the CPU boards as control inputs, and in response, the control circuitry causes the oscillator output selector to select the series of clock pulses having a frequency that is equal to or slower than the slowest preferred frequency. In an alternate embodiment, the control circuitry receives CPU types from the CPU boards as control inputs, and in response, the control circuitry causes the oscillator output selector to select a series of clock pulses having a frequency that will allow maximum total CPU clock frequency utilization.
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Citations
31 Claims
- 1. A central processing unit (CPU) circuit board comprising a CPU and first circuitry for outputting, at system reset time, control inputs to a system bus clock selection circuit operative to select an appropriate system bus clock from a plurality of available system bus clocks at the system reset time for a system bus, wherein the control inputs include the type of CPU, and wherein the system bus clock selection circuit and the system bus being coupled to each other and elements of a computer system within which the CPU circuit board is integrated.
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6. A computer system motherboard comprising:
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a plurality of oscillators operative to generate a plurality of series of clock pulses having different frequencies; and an oscillator output selector coupled to the oscillators operative to select an appropriate one of the series of clock pulses to be used as a system bus clock of a system bus of a computer system within which the computer system motherboard is integrated, wherein the selection of the series of clock pulses is based, at least in part, on the type of central processing unit(s) (CPU) of the computer system. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. An apparatus comprising:
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first circuitry operative to output at system reset time first control inputs; and second circuitry coupled to the first circuitry operative to receive the first control inputs, and operative to select an appropriate system bus clock from a plurality of available system bus clocks for a system bus in accordance to the received first control inputs, the system bus clock having a clock frequency based, at least in part, on the type of processor(s) of a system, as defined by the received first control inputs, the system bus being coupled to the second circuitry, and the system bus being an element of the system within which the processor(s) and the apparatus are integrated. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A computer system comprising;
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a first CPU board having a CPU and first circuitry for outputting at system reset time first control inputs including processor(s) type information; and a computer system motherboard coupled to the first CPU board having a system bus and system bus clock selection circuitry for selecting a system bus clock for the system based, at least in part, on the first control inputs received, wherein the system bus clock selection is optimal for resident CPU(s), as determined from the processor(s) type information. - View Dependent Claims (27, 28, 29, 30, 31)
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Specification