Bus arbitration system for multiprocessor architecture

• US 6,026,461 A
• Filed: 12/09/1998
• Issued: 02/15/2000
• Est. Priority Date: 08/14/1995
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Guyer, James M., Cox, Joseph, Gelinas, Robert G., Roux, Phil J., Sherman, Art A., Keating, David L., Yeung, Simon N., Radogna, Tom V., Hunt, Michael F., Baxter, William F., Gillott, Barry E., Truebenbach, Liz M., Pike, Rob J., Kimmell, Jeff S., Tucker, Doug J., Weiler, Pat J., Huck, Dan R., Heyda, Andrea, Valentine, Rob P., Sporer, Michael
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US09/208,139
• Time in Patent Office: 433 Days
• Field of Search: 710/107, 710/111-118, 710/240, 710/241, 710/243, 710/244
• US Class Current: 710/244
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Claims

1. A method of arbitrating requests for a system bus in a computer system by a plurality of system bus requesters comprising the steps:

establishing a window for simultaneously capturing all requests for said system bus, wherein said requests include information about a requested packet type, and an input queue state of said system bus requester;

capturing all said requests for said system bus during said window;

prioritizing said captured requests into high, medium, and low priority based on said information included in said captured requests;

examining potential system bus targets by their busy signals;

selecting one low priority requester, one medium priority requester, and one high priority requester as potential bus grant candidates;

choosing one of said selected low, medium, and high priority requesters by said requests, wherein high priority requests have priority over medium priority requests, which have priority over low priority requests, and medium priority requests are prioritized by time ordering; and

granting said system bus to said chosen requester.

2. The method of claim 1 wherein said step of selecting one low priority requester, one medium priority requester, and one high priority requester as potential bus grant candidates is based on said examined busy signals of potential bus targets and a shuffle code.

3. In a multi-processor computer system including a plurality of system busses, an arbitration system for arbitrating requests for one of said system buses by a plurality of system bus requesters comprising:

a system bus request input component, to accept requests;

a window defining component, to establish a window for capturing all requests to said system bus request input component, wherein said requests include information about a requested packet type, and an input queue state of said system bus requester;

a request prioritizing component to prioritize said captured requests into high, medium, and low priority based on said information included in said captured requests;

a selection component, to select one low priority request, one medium priority request, and one high priority request;

a granting component, to grant said system bus to a system bus requester corresponding to one of said selected low, medium, and high priority requests, wherein high priority requests have priority over medium priority requests, which have priority over low priority requests.

4. The arbitration system of claim 3 wherein medium priority requests are prioritized by time ordering.

5. The arbitration system of claim 3 wherein said selection component also examines potential system bus targets of requests, and does not select requests to a potential system bus target that is busy.

6. The arbitration system of claim 5 wherein said selection component also selects one low priority request, one medium priority request, and one high priority request based on a shuffle code.

7. The arbitration system of claim 3 wherein said multi-processor computer system is scalable in that additional processors may be added, with all processors having equal access to said plurality of system busses.

8. The arbitration system of claim 3 wherein said arbitration system is implemented as an ASIC (application specific integrated circuit) device.