Split embedded DRAM processor

• US 6,026,478 A
• Filed: 12/23/1997
• Issued: 02/15/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Dowling, Eric M.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/997,364
• Time in Patent Office: 784 Days
• Field of Search: 712/24, 712/35, 712/36, 712/34, 712/215
• US Class Current: 712/24
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

Claims

1. A split very long instruction word (VLIW) processing apparatus comprising:

a VLIW central processor comprising;

a set of functional units which receive a plurality of instructions for execution in parallel;

a first VLIW program cache which holds a collection of very long instruction words, each very long instruction word comprising a set of instruction fields, each instruction field comprising an instruction to be executed by a functional unit;

a dispatch unit which scans bit fields within said instruction fields to decide how many instructions to dispatch in parallel and to which functional unit to direct each instruction;

one or more register files coupled to said functional units;

an external memory interface which carries instructions and data from an external source; and

an on-board data memory coupled to said functional units, said register files, and said external memory interface,

wherein;

at least one of said functional units includes a branch processing unit which processes branch instructions;

said branch processing unit is coupled to a prefetch unit used to sequence said VLIW control words from said VLIW program cache or external memory; and

said branch processing unit is coupled to an external interface for transferring branch related information;

a VLIW extension processor which cooperates with said VLIW central processor to jointly execute a single VLIW program, said VLIW extension processor comprising;

a set of at least one functional unit which receives one or more instructions for execution in a given clock cycle;

a second VLIW program cache which holds a collection of very long instruction words, whereby each very long instruction word comprises one or more instruction fields, wherein each instruction field comprises an instruction to be executed by a functional unit; and

a second dispatch unit which scans bit fields within said instruction fields to decide how many instructions to dispatch in parallel and to which functional unit to direct each instruction,

wherein at least one of said functional units includes a second branch processing unit which processes branch instructions, said branch processing unit coupled to a prefetch unit which sequences VLIW control words from said second VLIW program cache, said branch processing unit coupled to a second external interface which transfers branch related information.

2. The split VLIW processing apparatus as defined in claim 1, further including an on-board dynamic random access memory (DRAM) coupled to said functional units, said on-board DRAM further being coupled to an externally controllable synchronous memory interface.

3. The split VLIW processing apparatus as defined in claim 2, wherein said DRAM is buffered via one of an active row sense amp techniques, an SRAM cache, or a data register file.

4. The split VLIW processing as defined in claim 1, wherein said first and second branch processing units simultaneously execute control dependent branches as encountered in looping without transferring branch related information across said second external interface.

5. The split VLIW processing apparatus as defined in claim 1, wherein:

only one of said first and second branch processing units simultaneously executes data dependent branches; and

the branch target address is passed to or from the said central VLIW from or to said VLIW extension processor.

6. The split VLIW processing as defined in claim 5, wherein the number of said data dependent branches requiring synchronization is minimized using conditional execution of instructions on said central VLIW processor and said VLIW extension processor.

7. The split VLIW processing apparatus as defined in claim 1, wherein:

said first and second prefetch units fetch a single very long instruction word which comprises a first portion stored in said first VLIW program cache which controls said first prefetch unit and a second portion stored in said second VLIW program cache which controls said second prefetch unit; and

information encoded into said first portion of said very long instruction word indicates whether said first prefetch unit is to dispatch a set of instructions each clock cycle or to insert delays between the dispatching of certain groups of instructions and information encoded into said second portion of said very long instruction word indicates whether said second prefetch unit is to dispatch a set of instructions each clock cycle or to insert delays between the dispatching of certain groups of instructions, said first and second prefetch units operating together in response to said first and second portions of said very long instruction word so as synchronize the dispatching of instructions in said central VLIW processor and said extension VLIW processor so as to conserve program memory space when the processing loads of said VLIW central processor and said VLIW extension processor are uneven.

8. The split VLIW processing apparatus as defined in claim 1, wherein said first branch processing unit sends a fork branch address to said second branch processing unit, said second branch processing unit responding to said fork branch address by forking an execution thread to a specified address so that said central VLIW processor and said VLIW extension processor execute separate instruction sequences in a decoupled manner.

9. The split VLIW processing apparatus as defined in claim 8, wherein, upon completion of said separate instruction sequences, said first and second branch processing units resynchronize by executing join instructions which cause said central VLIW processor and said extension VLIW processor to cease fetching instructions from a specified address until a synchronization signal has been received over said second external interface.

10. The split VLIW processing apparatus as defined in claim 1, further comprising a sequential access memory interface to said DRAM array so that said VLIW extension processor can directly control a frame buffer.