Data processing apparatus, system and method for if, then, else operation using write priority
First Claim
1. A method of conditional data processing operation comprising the steps of:
- setting a condition to either a first state or a second state;
performing a first arithmetic/logical operation and storing a first result in a first data register with a first write priority; and
conditionally moving predetermined data into said first data register if said condition has said first state with a second write priority, said second write priority of said conditional move being higher than said first write priority of said first arithmetic/logical operation whereby said first data register stores said predetermined data if said condition has said first state or said first result of said first arithmetic/logical operation if said condition does not have said first state.
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Abstract
A data processing apparatus employs write priority to permit a data processing apparatus to execute an if, then, else operation in a single instruction cycle. The data processing apparatus includes pipelined data unit (110) and address unit (120) operations. The address unit (120) data move operation has a higher write priority than the storing of the data unit (110) operation. The data unit (110) includes an arithmetic logic unit (230) that performs an unconditional operation with the result to be stored in a destination register (200). The address unit (120) sets the address for a data move operation to the same destination register (200). The data move operation is conditional upon the if condition set by the instruction and based upon a set of status bits in a status register (210). The status register (210) includes a plurality of status bits set corresponding to a prior arithmetic logic unit (230) result. The status bits preferably include a negative status bit, a carry status bit, an overflow status bit and a zero status bit. This address unit (120) data move operation, having a higher write priority than the data unit (110) operation, controls the data written into the destination register (200). If the status bits do not match the condition specified in the instruction, then the conditional data move does not take place and the results of the data unit operation are stored in the destination register (200).
52 Citations
96 Claims
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1. A method of conditional data processing operation comprising the steps of:
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setting a condition to either a first state or a second state; performing a first arithmetic/logical operation and storing a first result in a first data register with a first write priority; and conditionally moving predetermined data into said first data register if said condition has said first state with a second write priority, said second write priority of said conditional move being higher than said first write priority of said first arithmetic/logical operation whereby said first data register stores said predetermined data if said condition has said first state or said first result of said first arithmetic/logical operation if said condition does not have said first state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing apparatus comprising:
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a plurality of data registers; a status register storing at least one status bit; an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second inputs and generating a result at said output; and an instruction logic circuit connected to said plurality of data registers, said status register and said arithmetic logic unit, said instruction logic circuit controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction logic circuit in response to a first instruction controlling said arithmetic logic unit to form a first combination of inputs from first designated source data registers and store a first result in a first designated destination data register with a first write priority, and controlling said plurality of data registers to conditionally move predetermined data into said first designated destination data register if said at least one status bit in said status register has a predetermined state with a second write priority, said second write priority of said conditional move being higher than said first write priority of said first combination of inputs of said arithmetic logic unit whereby said first designated destination data register stores said predetermined data if said at least one status register has said predetermined state or said result of said first combination if said at least one status register does not have said predetermined state. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An data processing system comprising:
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an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a plurality of data registers, a status register storing at least one status bit, an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second inputs and generating a result at said output, and an instruction logic circuit connected to said plurality of data registers, said status register and said arithmetic logic unit, said instruction logic circuit controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction logic circuit in response to a first instruction controlling said arithmetic logic unit to form a first combination of inputs from first designated source data registers and store a first result in a first designated destination data register with a first write priority, and controlling said plurality of data registers to conditionally move predetermined data into said first designated destination data register if said at least one status bit in said status register has a predetermined state with a second write priority, said second write priority of said conditional move being higher than said first write priority of said first combination of inputs of said arithmetic logic unit whereby said first designated destination data register stores said predetermined data if said at least one status register has said predetermined state or said result of said first combination if said at least one status register does not have said predetermined state. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A method of conditional data processing operation comprising the steps of:
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a) setting a condition to either a first state or a second state; b) providing a first instruction type including an arithmetic logic unit code field indicating a first arithmetic/logical operation, a first source field indicating a first source data register from among a plurality of data registers, a second source field indicating a second source data register from among a plurality of data registers, a destination field indicating a first destination data register from among a plurality of data registers, at least one data transfer source field indicating a source of predetermined data for a first data transfer, a data transfer destination field indicating a second destination data register from among a plurality of data registers, a condition field indicating a state of said condition upon which a data transfer is conditional; c) specifying an if-then-else instruction in said first instruction type having said destination field indicating said first destination data register as a common destination data register and said data transfer destination field indicating said second destination data register as said common destination data register; and d) executing said if-then-else instruction by performing said first arithmetic/logical operation on data from said first and second source data registers and storing a first result in said common destination data register with a first write priority, and conditionally performing said first data transfer of said predetermined data into said common destination data register if said condition has said first state with a second write priority, said second write priority being higher than said first write priority thereby storing said predetermined data in said common destination data register if said condition has said first state or storing said first result of said first arithmetic/logical operation in said common destination data register if said condition does not have said first state. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. A data processing apparatus comprising:
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a plurality of data registers; a status register storing at least one status bit; an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second inputs and generating a result at said output; a source instructions including at least one if-then-else instruction having a first instruction type, said first instruction type including an arithmetic logic unit code field indicating a first arithmetic/logical operation, a first source field indicating a first source data register from among a plurality of data registers, a second source field indicating a second source data register from among a plurality of data registers, a destination field indicating a first destination data register from among a plurality of data registers, at least one data transfer source field indicating a source of predetermined data for a first data transfer, a data transfer destination field indicating a second destination data register from among a plurality of data registers, a condition field indicating a predetermined state of said at least one status bit upon which a data transfer is conditional, said at least one if-then-else instruction having said destination field indicating said first destination data register as a common destination data register and said data transfer destination field indicating said second destination data register as said common destination data register; an instruction logic circuit connected to said plurality of data registers, said status register, said arithmetic logic unit and said source of instructions, said instruction logic circuit controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction logic circuit in response to an if-then-else instruction controlling said arithmetic logic unit to form a first combination of said first and second source data registers corresponding to said specified first arithmetic/logical operation and store a first result in said common destination data register with a first write priority, and controlling said plurality of data registers to conditionally transfer predetermined data into said common destination data register if said at least one status bit in said status register has said predetermined state with a second write priority, said second write priority being higher than said first write priority whereby said common destination data register stores said predetermined data if said at least one status register has said predetermined state or said first result if said at least one status register does not have said predetermined state. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69)
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70. An data processing system comprising:
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an data system bus transferring data and addresses; a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus; an data processor circuit connected to said data system bus, said data processor circuit including a plurality of data registers; a status register storing at least one status bit; an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second inputs and generating a result at said output; a source instructions including at least one if-then-else instruction having a first instruction type, said first instruction type including an arithmetic logic unit code field indicating a first arithmetic/logical operation, a first source field indicating a first source data register from among a plurality of data registers, a second source field indicating a second source data register from among a plurality of data registers, a destination field indicating a first destination data register from among a plurality of data registers, at least one data transfer source field indicating a source of predetermined data for a first data transfer, a data transfer destination field indicating a second destination data register from among a plurality of data registers, a condition field indicating a predetermined state of said at least one status bit upon which a data transfer is conditional, said at least one if-then-else instruction having said destination field indicating said first destination data register as a common destination data register and said data transfer destination field indicating said second destination data register as said common destination data register; an instruction logic circuit connected to said plurality of data registers, said status register, said arithmetic logic unit and said source of instructions, said instruction logic circuit controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction logic circuit in response to an if-then-else instruction controlling said arithmetic logic unit to form a first combination of said first and second source data registers corresponding to said specified first arithmetic/logical operation and store a first result in said common destination data register with a first write priority, and controlling said plurality of data registers to conditionally transfer predetermined data into said common destination data register if said at least one status bit in said status register has said predetermined state with a second write priority, said second write priority being higher than said first write priority whereby said common destination data register stores said predetermined data if said at least one status register has said predetermined state or said first result if said at least one status register does not have said predetermined state. - View Dependent Claims (71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96)
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Specification