Configurable cryptographic processing engine and method

• US 6,026,490 A
• Filed: 08/01/1997
• Issued: 02/15/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lien, Ty Bao, Carswell, Phillip Anthony, Perea, William Louis, Johns-Vano, Kerry Lucille, Harrison, David Michael
• Primary Examiner(s): Hayes, Gail O.
• Assistant Examiner(s): Tucker, Christopher M.
• Application Number:
  US08/904,991
• Time in Patent Office: 928 Days
• Field of Search: 380/21, 380/3, 714/820, 714/821, 714/822, 714/824, 714/819
• US Class Current: 380/28
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A configurable cryptographic processing engine (100) provides high performance cryptographic processing support for symmetric combiner type cryptographic algorithms. As many as two independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A 3-stage instruction pipeline, dynamically configurable cryptographic co-processor (550), and 32-bit RISC based architecture support high performance cryptographic processing performance on the order of 60 Mbps aggregate throughput.

Claims

1. A configurable cryptographic engine comprising:

a first and second microcode memory for storing respective first and second channel programs;

a microsequencer for processing one of said channel programs; and

an execution unit having first and second registers for storing respectively, first and second context associated respectively with said first and second channel programs,

wherein said microsequencer configures said execution unit in response to said first channel program and said execution unit processes a first data unit in accordance with said first context and said first channel program, and

wherein said second channel program is loaded into said second microcode memory and said second context is loaded into said second registers during the processing of said first data unit for subsequently processing a second data by said execution unit.

2. A configurable cryptographic engine as claimed in claim 1 wherein said microsequencer further configures said execution unit in response to said second channel program and said execution unit processes a second data unit in accordance with said second context.

3. A configurable cryptographic engine as claimed in claim 1 wherein said first and second microcode memories, said microsequencer and said execution unit are fabricated on a single semiconductor substrate.

4. A configurable cryptographic engine as claimed in claim 1 further comprising:

a redundant microsequencer for processing said one channel program; and

a redundant execution unit having redundant first and second registers for storing respectively, said first and second context associated respectively with said first and second channel programs, wherein said redundant microsequencer configures said redundant execution unit in response to said first channel program, and said redundant execution unit processes said first data unit in accordance with said first context.

5. A configurable cryptographic engine as claimed in claim 4 further comprising:

first control logic for comparing output data of said microsequencer with output data of said redundant microsequencer; and

second control logic for comparing execution unit output data of said execution unit with execution unit output data of said redundant execution unit.

6. A configurable cryptographic engine as claimed in claim 5 wherein said first control logic has means for notifying an external host of discrepancies between said control unit output data of said microsequencer and said redundant microsequencer.

7. A configurable cryptographic engine as claimed in claim 5 wherein said second control logic has means for notifying an external host of discrepancies between said execution unit output data of said execution unit and said redundant execution unit.

8. A configurable cryptographic engine as claimed in claim 1 wherein said execution unit includes a cryptographic co-processor having said first and second registers contained therein, said cryptographic co-processor for performing combiner-type cryptographic operations on said first data unit.

9. In a configurable cryptographic engine comprised of first and second microcode memories, a microsequencer, an execution unit that includes a cryptographic co-processor, a method for processing data units comprising the steps of:

loading a first channel program into said first microcode memory;

loading first configuration bits associated with said first channel program into first registers associated with said execution unit;

loading first context of said first channel program into second registers associated with said cryptographic co-processor;

providing, by said microsequencer, first program parameters based on said first channel program to said cryptographic co-processor for configuring said cryptographic co-processor for an operation; and

performing, by said cryptographic co-processor, as configured with said first program parameters, said operation on a first data unit, said operation determined, at least in part, by said first channel program and said first context.

10. A method as claimed in claim 9 wherein the loading steps are performed during the processing of a second data unit by said cryptographic co-processor in accordance with a second channel program stored in said second microcode memory.

11. A method as claimed in claim 10 wherein second context associated with said second channel program is stored in third registers associated with execution unit, and

second configuration bits associated with said second channel program are stored in fourth registers associated with said execution unit,

said second context and said second configuration bits being used by said second channel program for processing said second data unit,

said second data unit being a prior data unit to said first data unit in a series of data units.

12. A method as claimed in claim 11 wherein said first channel program is comprised of a set of instructions, the method further comprising the steps of:

said microsequencer retrieving a first instruction from said set of instructions;

said microsequencer providing said first program parameters based on said first instruction to said cryptographic co-processor to configure said cryptographic co-processor for said operation; and

performing said operation on a first word of said first data unit, said operation determined, at least in part, by said first instruction, said first channel program, and said first context.

13. A method as claimed in claim 12 further comprising the steps of:

loading a third channel program into said second microcode memory;

loading third configuration bits associated with said third channel program into said fourth registers;

loading third context associated with said third channel program into said third registers; and

processing a third data unit by said execution unit in accordance with said third context and configuration bits after the processing of said first data unit,

the steps of loading said third channel program, said third configuration bits, and said third context being performed during the processing of said first data unit.

14. A method as claimed in claim 12 further comprising the steps of:

updating said first context in said second registers based on said operation performed on said first data unit;

repeating the steps of providing, performing said operation and updating said first context for other instructions of said set of instructions; and

for other words of said first data unit, repeating the steps of retrieving, providing, performing said operation and updating said first context to create an output data unit.

15. A method as claimed in claim 10 further comprising the step of loading an address of said first data unit into an address register, and reading said first data unit from a storage location indicated by said address.

16. A method as claimed in claim 10, wherein said configurable cryptographic engine further comprises a redundant microsequencer and a redundant execution unit, the method further comprising the steps of:

providing redundant program parameters by said redundant microsequencer to said redundant execution unit in accordance with said second channel program;

processing said first data unit in said redundant execution unit;

comparing said redundant program parameters with said first program parameters; and

notifying an external host of discrepancies between said redundant program parameters and said first program parameters.

17. In a configurable processing engine comprised of first and second microcode memories, a microsequencer, and an execution unit, wherein said first microcode memory has a first channel program stored therein, a method for processing data units comprising the steps of:

said microsequencer providing first configuration bits to said execution unit based on said first channel program;

said execution unit processing a first data unit based on said first configuration bits and first context associated with said first channel program, said first context being stored in a first context register associated with said execution unit; and

loading a second channel program into said second microcode memory during the performance of the processing step.

18. A method as claimed in claim 17 further comprising the steps of:

loading second context associated with said second channel program into a second context register associated with said execution unit during the performance of the processing step; and

said execution unit processing a second data unit based on said second context after the completion of the step of processing said first data unit.

19. A method as claimed in claim 18 further comprising the steps of:

loading a third channel program into said first microcode memory;

loading third context associated with said third channel program into said first context register; and

said execution unit processing a third data unit based on said third configuration bits and third context after the completion of the step of processing said second data unit, wherein

the loading said third channel program and third context steps being performed during the performance of the step of processing said second data unit.

20. A configurable cryptographic processing engine comprising:

a first control unit for performing a first channel program wherein said first channel program operates on a first data unit, said first control unit for performing a second channel program wherein said second channel program operates on a second data unit, subsequent to performing said first channel program;

a first memory for storing said first channel program;

a second memory for storing said second channel program, said second channel program being loaded in the second memory during the performance of said first channel program; and

a first execution unit for performing operations on selected portions of said first data unit based on the first channel program, said first execution unit for performing operations on selected portions of said second data unit based on the second channel program, subsequent to performing operations on said first data unit.

21. A configurable cryptographic processing engine as in claim 20 further comprising:

a second control unit for performing said first channel program, concurrently during the first control units'"'"' performance of the first channel program; and

a control unit check logic comparing output values of the first and second control units, and providing an alarm signal when the output values conflict.

22. A configurable cryptographic processing engine as in claim 21 comprising:

said second control unit for performing said second channel program, concurrently during the first control units'"'"' performance of the second channel program.

23. A configurable cryptographic processing engine as in claim 22 wherein each first and second control unit is comprised of:

a first microsequencer for performing fetch, execute, and write operations of each said first and second channel program, sending control data and receiving status data from said first execution unit.

24. A configurable cryptographic processing engine as in claim 20 further comprising:

a second execution unit for performing operations on selected portions of said first data unit, concurrently during the first execution units'"'"' performance of operations on selected portions of said first data unit; and

a execution unit check logic comparing output values of the first and second execution units, and providing an alarm signal when the output values conflict.

25. A configurable cryptographic processing engine as in claim 24 comprising:

said second execution unit for performing operations on selected portions of said second data unit, concurrently during the first execution units'"'"' performance of operations on selected portions of said second data unit.