Data processing system for controlling execution of a debug function and method thereof

• US 6,026,501 A
• Filed: 10/06/1997
• Issued: 02/15/2000
• Est. Priority Date: 08/30/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hohl, William A., Circello, Joseph C.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/944,655
• Time in Patent Office: 862 Days
• Field of Search: 395/183.14, 395/182.03, 395/182.06, 395/182.07, 395/182.08, 395/182.13, 395/182.21, 395/183.05, 371/21.1, 371/40.11, 371/40.13, 714/38, 714/5, 714/8-10, 714/15, 714/23, 714/29, 714/718, 714/763, 714/768
• US Class Current: 714/38.13
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Claims

1. A data processor, comprising:

a memory location in a memory circuit which is identified by an internal address;

a debug module, the debug module processing an external request to access the memory location of the data processor, the debug module asserting a bus request signal to initiate an access operation of the memory location and executing the access operation of the memory location upon receipt of a bus grant signal;

a central processing unit for controlling operation of the data processor, the central processing unit executing a plurality of data processing instructions using a pipeline method of operation wherein a first pipeline indicates a plurality of data processing instructions to be executed, the central processing unit selectively asserting a bus grant signal in response to the bus request signal when the plurality of data processing instructions have been executed;

bus means for communicating information between each of the debug module, the central processing unit, and the memory, the bus means communicating a data value stored at the memory location to the debug module when the bus grant signal is asserted.

2. The data processor of claim 1 wherein the external request is provided to the debug module by an external development system.

3. The data processor of claim 1 wherein the access operation of the memory location is a read access operation.

4. The data processor of claim 3 wherein the debug module further comprises:

a first address register for storing an address of the memory location; and

a first data register for storing the data value stored at the memory location in the memory circuit.

5. The data processor of claim 4 wherein the debug module provides the address of the memory location to the memory circuit using the bus means when the bus grant signal is asserted.

6. The data processor of claim 5 wherein the debug module stores the data value in the first data register after executing the read access operation.

7. The data processor of claim 1 wherein the access operation is a write access operation.

8. The data processor of claim 7 wherein the debug module further comprises:

a first data register for storing a write operand to be written to the memory location in the memory circuit.

9. The data processor of claim 1 further comprising:

a serial interface for receiving the external request from an external development system.

10. The data processor of claim 1 wherein the memory circuit is an internal register.

11. The data processor of claim 1 wherein the memory circuit may only be accessed internally.

12. A method for operating a data processor, comprising the steps of:

receiving a command to access a memory device from an external system;

receiving an address to access a memory location in the memory device from the external system;

decoding the command to determine a function to be executed by the data processor using a control circuit of a debug module of the data processor;

storing the address in a first address register in the debug module;

enabling the control circuit of the debug module to generate a bus request signal in a first logic state;

stalling an internal instruction pipeline of a central processing unit when a current plurality of pipelined instructions are executed and the bus request signal is in the first logic state;

enabling the central processing unit to generate a bus grant signal in a second logic state when the internal instruction pipeline of the central processing unit is stalled;

providing the address in the first address register in the debug module to the memory device when the bus grant signal is in the second logic state; and

accessing the memory location in the memory device to execute the function specified by the command provided by the external system.

13. The method of claim 12 wherein the memory device is not externally visible to the external system.

14. The method of claim 12 wherein a step of accessing the memory location in the memory device further comprises the steps of:

enabling the memory device to decode the address provided thereto;

reading a data value from the memory location in the memory device;

storing the data value in a first data register in the debug module; and

providing the data value to the external system.

15. The method of claim 12 wherein a serial interface serially receives the command and the address from the external system.

16. The method of claim 12 wherein a step of accessing the memory location in the memory device further comprises the steps of:

receiving a write operand from the external system;

storing the write operand in a first data register in the debug module;

enabling the memory device to decode the address provided thereto to indicate the memory location of the memory device;

providing the write operand to the memory device; and

storing the write operand to the memory location in the memory device.

17. The method of claim 16 wherein the step of accessing the memory location in the memory device is executed in a single bus timing cycle.

18. The method of claim 12 wherein the external system and the central processing unit selectively access the memory location in the memory device.

19. A method for operating a data processor, comprising the steps of:

receiving a command to access a memory device from an external system;

receiving an address to access a memory location in the memory device from the external system;

storing the address in a first address register in a debug module;

enabling a control circuit to generate a bus request signal;

enabling a bus granting unit to generate a bus grant signal when the bus is available;

providing the address in the first address register of the debug module to the memory device when the bus grant signal is received; and

accessing the memory location in the memory device to access the address specified by the command provided by the external system.

20. A data processor, comprising:

a memory location in a memory circuit, wherein the memory location is identified by an internal address;

a debug module, the debug module for processing an external request to access the memory location of the data processor, wherein the debug module asserts a bus request signal to initiate an access operation of the memory location and executes the access operation of the memory location upon receipt of a bus grant signal;

a central processing unit for controlling operation of the data processor, wherein the central processing unit asserting a bus grant signal in response to the bus request signal;

a bus for communicating information between each of the debug module, the central processing unit, and the memory.

21. The data processor of claim 20, further comprising:

the central processing unit having an instruction queue, wherein the bus grant signal is asserted when the instruction queue is empty.

22. The data processor of claim 21, further comprising:

the instruction queue receiving no new instructions after the receipt of a bus request.