Method and apparatus for real time two dimensional redundancy allocation

• US 6,026,505 A
• Filed: 10/16/1991
• Issued: 02/15/2000
• Est. Priority Date: 10/16/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Koch, Garrett Stephen, Hedberg, Erik Leigh
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US07/777,877
• Time in Patent Office: 3,044 Days
• Field of Search: 371/10.3, 371/21.1, 371/21.2, 714/711, 714/710, 714/702, 714/718, 714/719
• US Class Current: 714/711
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Claims

1. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising:

a memory array having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof,

first identifying means coupled to said memory array for identifying a given number of faulty cells along each of said column lines,

first register means disposed on said semiconductor chip having a number of registers equal to the number of redundant column lines,

second means coupled to said first identifying means for storing address signals of each of the column lines having said given number of faulty cells in said first register means, if a given number of faulty cells in one of the column lines is identified,

third identifying means coupled to said memory array for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,

second register means disposed on said semiconductor chip having a number of registers equal to the number of redundant row lines,

fourth means coupled to said third identifying means for storing address signals of each of the row lines having a faulty cell in said second register means,

fifth means coupled to said second register means for producing a given signal indicating that said second register means is filled to capacity,

sixth means responsive to said given signal for storing column line address signals of a faulty cell identified by said third identifying means in said first register means, if said first register means is not full, and

means coupled to said first and second register means for substituting said redundant column and row lines for the column and row lines having address signals stored in said first and second register means.

2. An array built in self test (ABIST) system as set forth in claim 1 wherein:

said first identifying means includes a counter,

said second means includes a first latch, and

said third identifying means includes row enable means coupled to an output of said first register means.

3. An array built in self test (ABIST) system as set forth in claim 2 wherein

said fourth means includes second and third latches,

said fifth means includes a circuit having an input coupled to an output of said second register means, and

said sixth means includes clock control means responsive to said signal.

4. An array built in self test (ABIST) system as set forth in claim 3 further including clock pulse source means selectively coupled to said first, second and third latches and wherein said counter has an input coupled to an output of said first register means and an output coupled to said first latch.

5. An array built in self test (ABIST) system as set forth in claim 3 wherein said first register means includes a plurality of EXCLUSIVE-OR circuits having an output coupled to an input of said row enable means.

6. An array built in self test (ABIST) system disposed on a single semiconductor chip comprising

a memory array disposed on said semiconductor chip having column lines and row lines with cells coupled to the lines at intersections thereof,

first means coupled to said memory array for searching for a given number of faulty cells along each of said column lines,

a first register disposed on said semiconductor chip,

means coupled to said first searching means for storing address signals of one of the column lines having said given number of faulty cells in said first register, if said first searching means locates one of the column lines having said given number of faulty cells,

second means coupled to said memory array for searching for a faulty cell along three of said row lines while masking the faulty cells having address signals of said column line stored in said first register,

second and third registers disposed on said semiconductor chip,

means coupled to said second searching means for storing address signals of each of two of the three row lines found to have a faulty cell in said second and third registers, and

means for storing the column line address signals of the faulty cell of the third of the three row lines in said first register if said first register is not storing another column address signal.

7. A built in self test system formed on a semiconductor chip comprising;

a memory array disposed on said semiconductor chip having column and row lines and cells located at the intersections of said lines and coupled thereto, a redundant column line and first and second redundant row lines,

circuit means coupled to said memory array for determining useful and faulty cells,

a data pattern generator coupled to said array and to said circuit means, and

two dimensional failed address register means disposed on said semiconductor chip having an input coupled to said circuit means, said two dimensional failed address register means including;

first identifying means coupled to said circuit means for identifying a given number of faulty cells along each of said column lines,

first register means,

means for applying address signals of said column lines to said first register means,

means coupled to said first identifying means for storing the address signals of each of the column lines having said given number of faulty cells in said first register means,

second identifying means coupled to said circuit means for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,

second register means,

means for applying address signals of said row lines to said second register means, and

means coupled to said second identifying means for storing the address signals of each of the row lines having a faulty cell in said second register means until said second register means is filled to capacity and then storing the address signals of the column line of any additional faulty cells identified in said row lines in said first register means.

8. A built in self test system as set forth in claim 7 further including means for substituting at least one of said redundant column line and said first and second redundant row lines for at least one of the column or row lines of said memory array having address signals stored in said first or second register means.

9. An array built in self test (ABIST) system comprising:

column re-timing means having column addresses applied to inputs thereof and having screen and non-screen outputs,

column fail address register means having inputs coupled to outputs of said column re-timing means for storing column addresses and for producing an address match signal and an enable signal,

counter means having a first input coupled to a cell pass/fail signal terminal, a second input having said address match signal applied thereto and a third input coupled to said non-screen output,

overflow circuit means for producing an overflow signal having a first input coupled to an output of said counter means and further inputs connected to a further output of said column fail address register means,

clock control means having an input coupled to said screen output,

a clock pulse source coupled to said column re-timing means, said clock control means, said column fail address register means, said counter means and said overflow circuit means,

row re-timing means having inputs connected to row address terminals and to said clock pulse source,

row fail address register means having inputs coupled coupled to outputs of said row re-timing means for storing row addresses and for producing a row full signal applied to said clock control means, and

row enable means having a first input for receiving said row enable signal, a second input coupled to said cell pass/fail signal terminal and a third input coupled to said non-screen output and an output connected to said row fail address register means,

said clock pulse source being coupled to said row re-timing means and to said row fail address register means.

10. An array built in self test (ABIST) system as set forth in claim 9 wherein said column and row fail address register means each include at least one register and a latch coupled to said register.

11. An array built in self test (ABIST) system as set forth in claim 9 wherein:

said column fail address register means includes first and second registers each having inputs coupled to the output of said column re-timing means and each producing an enable signal applied to said row enable means, and

said row fail address register means includes first, second, third and fourth registers each having inputs coupled to the outputs of said row re-timing means and each of said second and fourth registers producing a row full signal applied to said clock control means.