Methods of forming memory devices having protected gate electrodes

• US 6,027,971 A
• Filed: 07/16/1997
• Issued: 02/22/2000
• Est. Priority Date: 07/16/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Keon-soo, Cho, Kyung-rae, Kim, Jin-woo
• Primary Examiner(s): CHANG, JONI YUK YING
• Application Number:
  US08/895,513
• Time in Patent Office: 951 Days
• Field of Search: 438/257-267
• US Class Current: 438/257
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Methods of forming memory device having protected gate electrodes include the steps of forming protection layers on gate electrodes, word lines and related structures and then using these protected structures as etching and implantation masks to reliably form semiconductor regions in a substrate. In particular, methods of forming integrated circuit memory devices preferably include the steps of patterning a field oxide isolation region at a face of a semiconductor substrate to define an active region therein and then forming a gate electrode of a memory device on the active region. Word lines are also formed on the gate electrode and on the field oxide isolation region. A first protection layer, comprising a material which can preferably be used as a selective etching mask, is also formed on an upper surface of the word line to protect the word line. The field oxide isolation region, which may be a relatively thick silicon dioxide layer, is then preferably etched to expose the face of the substrate. Here, the etching step is performed using the protected word line as an etching mask.

Claims

1. A method of forming an integrated circuit memory device, comprising the steps of:

patterning a field oxide isolation region at a face of a semiconductor substrate to define an active region therein;

forming a gate electrode of a memory device on the active region;

forming a word line on the field oxide isolation region and on the gate electrode;

forming a first protection layer on an upper surface of the word line;

implanting source and drain region dopants of first conductivity type into the active region, using the first protection layer as an implant mask;

then

etching the field oxide isolation region to expose the face of the substrate, using the first protection layer as an etching mask; and

implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region therein which is electrically coupled to the memory device, using the first protection layer as an implant mask.

2. The method of claim 1, wherein said step of etching the field oxide isolation region is preceded by the step of forming a second protection layer on sidewalls of the word line.

3. The method of claim 2, wherein said steps of forming a gate electrode, a word line and a first protection layer comprise the steps of:

forming a first gate insulating layer on the face of the substrate, opposite the active region;

forming a first conductive layer on the first gate insulating layer, opposite the active region;

forming a second gate insulating layer on the first conductive layer, opposite the first gate insulating layer;

forming a second conductive layer on the second gate insulating layer, opposite the first conductive layer;

forming a third gate insulating layer on the second conductive layer, opposite the second gate insulating layer;

patterning the third gate insulating layer as the first protection layer and the second conductive layer as the word line; and

patterning the first conductive layer to define a floating gate electrode.

4. The method of claim 3, wherein the second gate insulating layer comprises first and second oxide insulating layers and a nitride insulating layer therebetween.

5. The method of claim 4, wherein the third gate insulating layer comprises a material selected from the group consisting of silicon nitride and silicon oxynitride.

6. The method of claim 5, wherein said step of etching the field oxide isolation region is preceded by the step of thermally treating the substrate at a temperature greater than about 900°

C. to drive-in the implanted source and drain region dopants of first conductivity type into the active region and form a birds beak oxide extension having a thickness in a range between about 200 and 1,000 Å

, between the floating gate electrode and the face.

7. The method of claim 6, wherein said step of forming a second protection layer on sidewalls of the word line comprises depositing a layer of material selected from the group consisting of silicon nitride and silicon oxynitride, on the substrate;

and then anisotropically etching the deposited layer of material to define insulating spacers on sidewalls of the floating gate electrode and the word line.

8. The method of claim 7, wherein said step of etching the field oxide isolation region comprises etching the field oxide isolation region using a plasma and the first protection layer and insulating spacers as an etching mask;

and wherein said step of implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region is followed by the step of thermally treating the substrate at a temperature greater than about 900°

C. to repair etching damage in the substrate.

9. A method of forming nonvolatile memory device, comprising the steps of:

patterning a field oxide isolation region at a face of a semiconductor substrate to define an active region therein;

forming first and second floating gate electrodes of respective first and second EEPROM memory cells, on the active region;

forming a word line on the field oxide isolation region and on the first and second floating gate electrodes;

forming a first protection layer on an upper surface of the word line;

implanting source and drain region dopants of first conductivity type into the active region, using the first protection layer as an implant mask;

then

etching the field oxide isolation region to expose the face of the substrate, using the first protection layer as an etching mask; and

implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region therein which is electrically coupled to the first and second EEPROM memory cells, using the first protection layer as an implant mask.

10. The method of claim 9, wherein said step of etching the field oxide isolation region is preceded by the step of forming a second protection layer on sidewalls of the word line.

11. The method of claim 10, wherein said steps of forming a first floating gate electrode, a word line and a first protection layer comprise the steps of:

forming a first gate insulating layer on the face of the substrate, opposite the active region;

forming a first conductive layer on the first gate insulating layer, opposite the active region;

forming a second gate insulating layer on the first conductive layer, opposite the first gate insulating layer;

forming a second conductive layer on the second gate insulating layer, opposite the first conductive layer;

forming a third gate insulating layer on the second conductive layer, opposite the second gate insulating layer;

patterning the third gate insulating layer as the first protection layer and the second conductive layer as the word line; and

patterning the first conductive layer as the first floating gate electrode.

12. The method of claim 11, wherein the second gate insulating layer comprises first and second oxide insulating layers and a nitride insulating layer therebetween.

13. The method of claim 12, wherein the third gate insulating layer comprises a material selected from the group consisting of silicon nitride and silicon oxynitride.

14. The method of claim 13, wherein said step of etching the field oxide isolation region is preceded by the step of thermally treating the substrate at a temperature greater than about 900°

C. to drive-in the implanted source and drain region dopants of first conductivity type into the active region and form a birds beak oxide extension having a thickness in a range between about 200 and 1,000 Å

, between the first floating gate electrode and the face.

15. The method of claim 14, wherein said step of forming a second protection layer on sidewalls of the word line comprises depositing a layer of material selected from the group consisting of silicon nitride and silicon oxynitride, on the substrate;

and then anisotropically etching the deposited layer of material to define insulating spacers on sidewalls of the first floating gate electrode and the word line.

16. The method of claim 15, wherein said step of etching the field oxide isolation region comprises etching the field oxide isolation region using a plasma and the first protection layer and insulating spacers as an etching mask;

and wherein said step of implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region is followed by the step of thermally treating the substrate at a temperature greater than about 900°

C. to repair etching damage in the substrate.

17. A method of forming an integrated circuit memory device, comprising the steps of:

forming a field oxide isolation region at a face of a semiconductor substrate to define an active region therein;

forming a gate electrode of a memory device on the active region;

forming a word line on the field oxide isolation region and on the gate electrode;

forming a first protection layer comprising a material selected from the group consisting of silicon nitride and silicon oxynitride, on an upper surface of the word line;

etching the field oxide isolation region to expose the face of the substrate, using the first protection layer as an etching mask that protects the word line; and

implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region therein which is electrically coupled to the memory device, using the first protection layer as an implant mask that protects the word line from implant damage.

18. The method of claim 17, wherein said step of etching the field oxide isolation region is preceded by the step of forming a second protection layer on sidewalls of the word line.

19. The method of claim 18, wherein said steps of forming a gate electrode, a word line and a first protection layer comprise the steps of:

forming a first gate insulating layer on the face of the substrate, opposite the active region;

forming a first conductive layer on the first gate insulating layer, opposite the active region;

forming a second gate insulating layer on the first conductive layer, opposite the first gate insulating layer;

forming a second conductive layer on the second gate insulating layer, opposite the first conductive layer;

forming a third gate insulating layer on the second conductive layer, opposite the second gate insulating layer;

patterning the third gate insulating layer as the first protection layer, patterning the second conductive layer as the word line and patterning the second gate insulating layer; and

patterning the first conductive layer to define a floating gate electrode.

20. The method of claim 19, wherein the second gate insulating layer comprises first and second oxide insulating layers and a nitride insulating layer therebetween.

21. The method of claim 20, wherein said step of etching the field oxide isolation region is preceded by the steps of implanting dopants of first conductivity type into the active region, using the patterned third gate insulating layer as an implant mask;

and then thermally treating the substrate at a temperature greater than about 900°

C. to drive-in the implanted dopants of first conductivity type into the active region and form a birds beak oxide extension having a thickness in a range between about 200 and 1,000 Å

, between the floating gate electrode and the face.

22. The method of claim 21, wherein said step of forming a second protection layer on sidewalls of the word line comprises depositing a layer of material selected from the group consisting of silicon nitride and silicon oxynitride, on the substrate;

and then anisotropically etching the deposited layer of material to define insulating spacers on sidewalls of the floating gate electrode and the word line.

23. The method of claim 22, wherein said step of etching the field oxide isolation region comprises etching the field oxide isolation region using a plasma and the first protection layer and insulating spacers as an etching mask;

and wherein said step of implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region is followed by the step of thermally treating the substrate at a temperature greater than about 900°

C. to repair etching damage in the substrate.

24. A method of forming nonvolatile memory device, comprising the steps of:

forming a field oxide isolation region at a face of a semiconductor substrate to define an active region therein;

forming first and second floating gate electrodes of respective first and second EEPROM memory cells, on the active region;

forming a word line on the field oxide isolation region and on the first and second floating gate electrodes;

forming a first protection layer comprising a material selected from the group consisting of silicon nitride and silicon oxynitride, on an upper surface of the word line;

etching the field oxide isolation region to expose the face of the substrate, using the first protection layer as an etching mask that protects the word line; and

implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region therein which is electrically coupled to the first and second EEPROM memory cells, using the first protection layer as an implant mask that protects the word line from implant damage.

25. The method of claim 24, wherein said step of etching the field oxide isolation region is preceded by the step of forming a second protection layer on sidewalls of the word line.

26. The method of claim 25, wherein said steps of forming a first floating gate electrode, a word line and a first protection layer comprise the steps of:

forming a first gate insulating layer on the face of the substrate, opposite the active region;

forming a first conductive layer on the first gate insulating layer, opposite the active region;

forming a second gate insulating layer on the first conductive layer, opposite the first gate insulating layer;

forming a second conductive layer on the second gate insulating layer, opposite the first conductive layer;

forming a third gate insulating layer on the second conductive layer, opposite the second gate insulating layer;

patterning the third gate insulating layer as the first protection layer, patterning the second conductive layer as the word line and patterning the second gate insulating layer; and

patterning the first conductive layer as the first floating gate electrode.

27. The method of claim 26, wherein the second gate insulating layer comprises first and second oxide insulating layers and a nitride insulating layer therebetween.

28. The method of claim 27, wherein said step of etching the field oxide isolation region is preceded by the steps of implanting dopants of first conductivity type into the active region, using the first protection layer as an implant mask;

and then thermally treating the substrate at a temperature greater than about 900°

C. to drive-in the implanted dopants of first conductivity type into the active region and form a birds beak oxide extension having a thickness in a range between about 200 and 1,000 Å

, between the first floating gate electrode and the face.

29. The method of claim 28, wherein said step of forming a second protection layer on sidewalls of the word line comprises depositing a layer of material selected from the group consisting of silicon nitride and silicon oxynitride, on the substrate;

and then anisotropically etching the deposited layer of material to define insulating spacers on sidewalls of the first floating gate electrode and the word line.

30. The method of claim 29, wherein said step of etching the field oxide isolation region comprises etching the field oxide isolation region using a plasma and the first protection layer and insulating spacers as an etching mask;

and wherein said step of implanting dopants of first conductivity type into the exposed face of the substrate to define a common source region is followed by the step of thermally treating the substrate at a temperature greater than about 900°

C. to repair etching damage in the substrate.