Semiconductor device contact registration structure

• US 6,028,325 A
• Filed: 12/09/1996
• Issued: 02/22/2000
• Est. Priority Date: 12/09/1995
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Guay, John
• Application Number:
  US08/762,617
• Time in Patent Office: 1,170 Days
• Field of Search: 257/49, 257/66, 257/410, 257/774
• US Class Current: 257/66
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31687 by anodic oxidation
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

An aluminum pattern is formed at the same time as a gate electrode, and anodic oxide films are formed on the surfaces of the aluminum pattern and the gate electrode. After an interlayer insulating film is formed, a contact hole is formed through it. Even if the contact hole is deviated from the intended position, there occurs no failure because of the existence of the aluminum pattern on which the anodic oxide film is formed.

Claims

1. A semiconductor device comprising:

a semiconductor formed on a substrate;

an insulating film formed on the semiconductor;

a gate electrode formed on the insulating film;

a plurality of patterns formed on the insulating film over the same semiconductor that supports the rate electrode and comprising a material capable of being anodized, wherein at least one pattern is located over an edge of the semiconductor and is displaced and insulated from the gate electrode so as to determine and confine a position of a contact hole to the semiconductor between the gate electrode and said at least one pattern without exposing the substrate; and

anodic oxide films formed on respective surfaces of the plurality of patterns.

2. A semiconductor device comprising:

a semiconductor formed over a substrate;

an insulating film formed on the semiconductor;

a plurality of patterns formed on the insulating film over the same semiconductor that supports a gate electrode and comprising a material capable of being anodized, at least one pattern serving as the gate electrode, and at least one other pattern located partially over an edge of the semiconductor and partially over a portion of the substrate adjacent to the semiconductor, wherein the at least one other pattern is displaced and isolated from said gate electrode to confine a position of a contact between the at least one other pattern and said gate electrode over the semiconductor; and

anodic oxide films formed on respective surfaces of the plurality of patterns.

3. The device of claim 2, wherein the semiconductor is a thin-film semiconductor formed on an insulative surface of the substrate.

4. The device of claim 2, further comprising source and drain regions in the semiconductor located relative to the gate electrode to form a thin-film transistor, and wherein the contact between the at least one other pattern and said gate electrode is in contact with one of the source and drain regions.

5. A semiconductor device comprising:

a semiconductor film;

an insulating film formed on said semiconductor film;

a pair of patterns and a gate electrode formed on said insulating film, wherein each of said pair of patterns and said gate electrode is covered with an anodic oxide film and said pair of patterns have a function of determining a position of a contact to said semiconductor film;

a first interlayer insulating film formed on said pair of patterns and said gate electrode, wherein said first interlayer insulating film and said insulating film define a contact hole therethrough between said pair patterns;

a source line formed on said first interlayer insulating film and in contact with said semiconductor film through said contact hole; and

a second interlayer insulating film formed on said first interlayer insulating film and said source line.

6. The device of claim 5, wherein said contact hole has a first portion in said first interlayer insulating film and a second portion between said pair of patterns and in said insulating film, said first portion configured to be larger than said second portion.

7. A semiconductor device comprising:

a semiconductor film;

an insulating film formed on said semiconductor film;

a pair of patterns formed on said insulating film for determining a position of a contact to said semiconductor film, each of said pair of patterns covered with an anodic oxide film;

a first interlayer insulating film formed on said pair of patterns;

a second interlayer insulating film formed on said first interlayer insulating film, wherein said insulating film and said first and second interlayer insulating films define a contact hole therethrough that is located between said pair of patterns to expose a portion of said semiconductor film; and

a pixel electrode formed on said second interlayer insulating film and located to contact said exposed portion of said semiconductor film through said contact hole.

8. The device of claim 7 wherein said contact hole has a first portion in said first and second interlayer insulating films and a second portion between said pair of patterns and in said insulating film, said first portion configured to be larger than said second portion.