Semiconductor device having a stress relieving mechanism

• US 6,028,364 A
• Filed: 03/19/1997
• Issued: 02/22/2000
• Est. Priority Date: 09/20/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Ogino, Masahiko, Akahoshi, Haruo, Nagai, Akira, Tanaka, Naotaka, Takahashi, Akio, Miwa, Takao, Ishii, Toshiaki, Eguchi, Shuji, Segawa, Masanori, Anjou, Ichirou
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/809,233
• Time in Patent Office: 1,070 Days
• Field of Search: 257/706, 257/737, 257/778, 257/700, 257/714, 257/692, 257/712, 257/698, 257/717, 257/722, 257/723, 257/738, 257/668, 257/758, 257/750, 257/701, 361/764, 361/783, 361/707, 361/792, 361/730, 361/765, 361/808, 174/256, 174/255
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device has a multi-layered wiring structure having a conductor layer to be electrically connected to a packaging substrate, the structure being provided on a circuit formation surface of a semiconductor chip; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate, after packaging thereof, and multiple wiring layers. In this semiconductor device, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase the signal speed; the distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in the improved connection reliability; and the number of terminals per unit is increased because of elimination of wire bonding.

Claims

1. A semiconductor device comprising:

a multi-layered wiring structure comprising multiple wiring layers, the wiring structure having a first side with a surface provided on a circuit formation surface of a semiconductor chip; and

ball-like terminals, which are for electrical connection to a wiring substrate, are disposed in a grid array on another surface corresponding to a second, opposing side of said multi-layered wiring structure,

wherein said multi-layered wiring structure further comprises a buffer layer with a low elasticity for relieving a thermal stress produced between said semiconductor chip and said wiring substrate after packaging thereof.

3. A semiconductor device according to claim 1, wherein two or more semiconductor chips are provided on one multi-layered wiring structure.

4. A semiconductor device according to claim 1, wherein said multi-layered wiring structure has three or more of conductive layers, and said conductive layers comprise a ground layer, a power supply layer, and a wiring layer.

5. A semiconductor device according to claim 1, wherein said buffer layer comprises an insulator and a plurality of conductors penetrating said insulator, said conductors being formed in the shape of multiple wires projecting in the direction perpendicular to the circuit formation surface of said semiconductor chip, and said insulator being made of a high molecular organic material having a modulus of elasticity of 10 kg/mm² or less.

6. A semiconductor device according to claim 1, wherein said buffer layer comprises an insulator and a plurality of conductors penetrating said insulator, said conductors being formed in the shape of multiple wires projecting in the direction perpendicular to the circuit formation surface of said semiconductor chip, said insulator being formed of a polyimide insulating film.

7. A semiconductor device according to claim 1, wherein said buffer layer comprises an insulator and a plurality of conductors penetrating said insulator, said conductors being formed in the shape of multiple wires projecting in the direction perpendicular to the circuit formation surface of said semiconductor chip, said insulator being made of a material selected from elastomers and low elastic engineering plastics each having a modulus of elasticity of 10 kg/mm² or less.

8. A semiconductor device according to claim 1, wherein said buffer layer comprises an insulator and a plurality of conductors penetrating said insulator, said conductors being formed in the shape of multiple wire projecting in the direction perpendicular to the circuit formation surface of said semiconductor chip, said insulator being made of a material selected from silicon base elastomers and fluorine base elastomers, each having a modulus of elasticity of 10 kg/mm², and a combination thereof.

9. A semiconductor device according to claim 1, wherein said interlayer insulating film in said multiple wiring layers is made of a high molecular organic material having a modulus of elasticity of 10 kg/mm² or less.

10. A semiconductor device according to claim 1 or 2, wherein said interlayer insulating film in said multiple wiring layers is made of a polyimide insulating film.

11. A semiconductor device according to claim 1, wherein said interlayer insulating film in said multiple wiring layers is made of a material selected from elastomers and low elastic engineering plastics, each having a modulus of elasticity of 10 kg/mm² or less.

12. A semiconductor device according to claim 1, wherein said interlayer insulating film in said multiple wiring layers is made of a material selected from silicon base elastomers and fluorine base elastomers, each having a modulus of elasticity of 10 kg/mm² or less, and the combination thereof.

13. A semiconductor device according to claim 1, wherein each said ball-like terminals provided for connection of said multi-layered wiring structure to said packaging substrate are made of a metal material selected from solder alloys containing tin, lead, and zinc;

silver;

copper;

gold; and

said metal material covered with gold.

14. A semiconductor device according to claim 1, wherein said semiconductor chip has a heat spreader for heat radiation.

15. A semiconductor device according to claim 14, wherein said heat spreader is so configured that said semiconductor chip or said semiconductor chip connected with said buffer layer is buried in said heat spreader.

2. A semiconductor device comprising:

a multi-layered wiring structure comprising multiple wiring layers, the wiring structure having a first side with a surface provided on a circuit formation surface of a semiconductor chip; and

ball-like terminals, which are for electrical connection to a wiring substrate, are disposed in a grid array on another surface corresponding to a second, opposing side of said multi-layered wiring structure,

wherein an interlayer insulating film in said multiple wiring layers for transmitting an electrical signal of said multi-layered wiring structure is made of a material capable with a low elasticity for relieving a thermal stress produced between said semiconductor chip and said wiring substrate after packaging thereof.

16. A packaging structure comprising:

a multi-layered wiring structure comprising multiple wiring layers, the wiring structure having a first side with a surface provided on a circuit formation surface of a semiconductor chip; and

ball-like terminals, which are for electrical connection and for mounting on a multi-layer wiring substrate, are disposed in a grid array on another surface corresponding to a second, opposing side of said multi-layered wiring structure,

wherein said multi-layered wiring structure further comprises a buffer layer with a low elasticity for relieving a thermal stress produced between said semiconductor chip and the wiring substrate, after packaging thereof.

18. A packaging structure according to claim 16, wherein said buffer layer comprises an insulator and a plurality of conductors penetrating said insulator, said conductors being formed in the shape of multiple wire projecting in the direction perpendicular to the circuit formation surface of said semiconductor chip, said insulator being made of a high molecular organic material having a modulus of elasticity of 10 kg/mm² or less.

19. A packaging structure according to claim 16, wherein said interlayer insulating film in said multiple wiring layers is made of a high molecular organic material having a modulus of elasticity of 10 kg/mm² or less.

17. A packaging structure comprising:

a multi-layered wiring structure comprising multiple wiring layers, the wiring structure having a first side with a surface provided on a circuit formation surface of a semiconductor chip; and

ball-like terminals, which are for electrical connection and for mounting on a multi-layer wiring substrate, are disposed in a grid array on another surface corresponding to a second, opposing side of said multi-layered wiring structure,

wherein an interlayer insulating film in said multiple wiring layers for transmitting an electrical signal of said multi-layered wiring structure is made of a material with a low elasticity for relieving a thermal stress produced between said semiconductor chip and the wiring substrate after packaging thereof.