Three-statable net driver for antifuse field programmable gate array

• US 6,028,444 A
• Filed: 12/20/1996
• Issued: 02/22/2000
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Wong, Richard J., Kolze, Paige A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/771,471
• Time in Patent Office: 1,159 Days
• Field of Search: 326/38-41, 326/44, 326/49, 326/83, 326/86, 326/102, 326/103, 326/45, 326/50, 326/87, 327/525
• US Class Current: 326/38
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.

Claims

1. A programmable device, comprising:

a logic module comprising;

an internal net driver having a first transistor and a second transistor, the first transistor having a source and drain of a first conductivity type, the second transistor having a source and a drain of a second conductivity type opposite the first conductivity type, the drain of the first transistor being coupled to the drain of the second transistor, the source and drain of the first transistor being disposed in a well, the source of the first transistor being coupled to a first supply voltage Vcc1, the source and drain of the second transistor not being disposed in the well;

a third transistor having a source and a drain of the first conductivity type, a gate electrode of the third transistor being coupled within the logic module to a DC voltage, the gate electrode of the third transistor not being coupled to gate electrode of the first transistor, the gate electrode of the third transistor not being coupled to a gate electrode of the second transistor, the source and drain of the third transistor being disposed in the well, the source of the third transistor being coupled to the first supply voltage Vcc1; and

a fourth transistor having a source and a drain of the second conductivity type, a gate electrode of the fourth transistor being coupled within the logic module to a second DC voltage, the gate electrode of the fourth transistor not being coupled to the gate electrode of the first transistor, the gate electrode of the fourth transistor not being coupled to the gate electrode of the second transistor, the source and drain of the fourth transistor not being disposed in the well;

wherein the source of the first transistor and the third transistor are not coupled to an optional second supply voltage Vcc2, the first supply voltage Vcc1 being greater than the second supply voltage Vcc2;

a first routing conductor coupled to the drain of the first transistor and to the drain of the second transistor;

a second routing conductor; and

an antifuse for coupling the first routing conductor to the second routing conductor, the first routing conductor, the second routing conductor and the antifuse being part of a programmable interconnect structure of the programmable device.

2. The programmable device of claim 1, wherein the first conductivity type is P-type semiconductor, and wherein the well is of N-type semiconductor.

3. The programmable device of claim 1, wherein the first conductivity type is N-type semiconductor, and wherein the well is of P-type semiconductor.

4. The programmable device of claim 1, wherein the internal net driver is a three-statable output driver, the drains of the first and second transistors being coupled to the first routing conductor via a protection transistor, a first electrode of the protection transistor being coupled to the drain of the first transistor and to the drain of the second transistor, a second electrode of the protection transistor being coupled to the first routing conductor.

5. The programmable device of claim 1, wherein the internal net driver is a three-statable output driver, the drains of the first and second transistors being coupled to the first routing conductor via a first protection transistor and a second protection transistor, a first electrode of the first protection transistor being coupled to the drain of the first transistor and to the drain of the second transistor, a second electrode of the first protection transistor being coupled to the first routing conductor, a first electrode of the second protection transistor being coupled to the drain of the first transistor and to the drain of the second transistor, a second electrode of the second protection transistor being coupled to the first routing conductor.

6. The programmable device of claim 1, wherein the drain of the third transistor is not coupled to the drain of the first transistor, and wherein the drain of the fourth transistor is not coupled to the drain of the second transistor.

7. The programmable device of claim 1, wherein there are no transistors disposed between the first and third transistors, and wherein there are no transistors disposed between the second and third transistors.

8. The programmable device of claim 7, wherein the gate electrode of the first transistor extends parallel to the gate electrode of the third transistor.

9. The programmable device of claim 1, wherein the drain of the third transistor is coupled to the source of the third transistor, and wherein the drain of the fourth transistor is coupled to the source of the fourth transistor.

10. The programmable device of claim 1, wherein the antifuse is a programmed antifuse.

11. The programmable device of claim 1, wherein the antifuse is a programmed antifuse which has a maximum permissible operating current, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at a first supply voltage Vcc1, the peak operating current flowing through the programmed antifuse being less than the maximum permissible operating current.

12. The programmable device of claim 1, further comprising:

option means for coupling the source of the third transistor to the drain of the third transistor, and for coupling the source of the fourth transistor to the drain of the fourth transistor.

13. The programmable device of claim 12, wherein the option means is also for coupling the gate electrode of the third transistor and the gate electrode of the fourth transistor to ground potential, the DC voltage and the second DC voltage being ground potential.

14. The programmable device of claim 12, wherein had the third transistor been coupled in parallel with the first transistor and had the fourth transistor been coupled in parallel with the second transistor, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at a second supply voltage Vcc2 would not be greater than the maximum permissible operating current, the first supply voltage Vcc1 being greater than the second supply voltage Vcc2.

15. The programmable device of claim 14, wherein the first supply voltage Vcc1 is about 5 volts and the second supply voltage Vcc2 is about 3 volts.

16. A programmable device, comprising:

a logic module comprising;

an output driver having a first transistor and a second transistor, the first transistor having a source and drain of a first conductivity type, the second transistor having a source and drain of a second conductivity type opposite the first conductivity type, the drain of the first transistor being coupled to the drain of the second transistor, the source and drain of the first transistor being disposed in a well, the source and drain of the second transistor not being disposed in the well;

a third transistor having a source and a drain of the first conductivity type, a gate electrode of the third transistor being coupled within the logic module to a DC voltage, the gate electrode of the third transistor not being coupled to gate electrode of the first transistor, the gate electrode of the third transistor not being coupled to a gate electrode of the second transistor, the source and drain of the third transistor being disposed in the well; and

a fourth transistor having a source and a drain of the second conductivity type, a gate electrode of the fourth transistor being coupled within the logic module to a second DC voltage, the gate electrode of the fourth transistor not being coupled to the gate electrode of the first transistor, the gate electrode of the fourth transistor not being coupled to the gate electrode of the second transistor, the source and drain of the fourth transistor not being disposed in the well;

a first routine conductor coupled to the drain of the first transistor and to the drain of the second transistor;

a second routing conductor; and

an antifuse for coupling the first routing conductor to the second routing conductor, the antifuse being a programmed antifuse which has a maximum permissible operating current, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at a first supply voltage Vcc1, the peak operating current flowing through the programmed antifuse being less than the maximum permissible operating current,

wherein had the third transistor been coupled in parallel with the first transistor and had the fourth transistor been coupled in parallel with the second transistor, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at the first supply voltage Vcc1 would be greater than the maximum permissible operating current.

17. The programmable device of claim 16, wherein the first supply voltage Vcc1 is about 5 volts.

18. The programmable device of claim 16, wherein the DC voltage and the second DC voltage are the same DC voltage.

19. A field programmable gate array, comprising:

a programmable interconnect structure comprising routing conductors and antifuses, the antifuses having a maximum permissible operating current; and

means for driving a net in the programmable interconnect structure at a first supply voltage Vcc1 using a first transistor and second transistor coupled in parallel so that the peak operating current flowing through the antifuses is less than the maximum permissible operating current if a first mask option is used, and for driving the net at a second supply voltage Vcc2 with the first transistor and without the second transistor so that the peak operating current flowing through the antifuses is less than the maximum permissible operating current if a second mask option is used, wherein the first supply voltage Vcc1 is less than the second supply voltage Vcc2.

20. The field programmable gate array of claim 19, wherein current flows from source to drain through the first transistor and from source to drain through the second transistor when the first mask option is used, and wherein current flows from source to drain through the first transistor but not from source to drain through the second transistor when the second mask option is used.

21. The field programmable gate array of claim 19, the field programmable gate array having a first logic module and a second logic module, the means being located in the first logic module, the net extending from the means of the first logic module and to an input of the second logic module, the net comprising routing conductors and an antifuse.

22. The field programmable gate array of claim 21, wherein the antifuse is an amorphous silicon antifuse.

23. A method, comprising:

using a first mask option to provide an effective pulldown transistor size A of a net driver in a first field programmable gate array structure having antifuses;

using a second mask option to provide an effective pulldown transistor size B of a net driver in a second field programmable gate array structure having antifuses;

operating the first field programmable gate array structure at a first supply voltage Vcc1; and

operating the second field programmable gate array structure at a second supply voltage Vcc2, Vcc1 being greater than Vcc2, effective transistor size A being smaller than effective transistor size B, the net driver in the first field programmable gate array structure being substantially identical to the net driver in the second field programmable gate array structure but for differences in a single interconnect layer.

24. The method of claim 23, wherein the single interconnect layer is a metal layer.

25. The method of claim 23, wherein the net driver of the first field programmable gate array outputs a first operating current during the operating at supply voltage Vcc1, and wherein the net driver of the second field programmable gate array outputs a second operating current during the operating at supply voltage Vcc2, the first and second operating currents being substantially equal.

26. A method, comprising:

using a first mask option to provide an effective pullup transistor size A of a net driver in a first field programmable gate array structure having antifuses;

using a second mask option to provide an effective pullup transistor size B of a net driver in a second field programmable gate array structure having antifuses;

operating the first field programmable gate array structure at a first supply voltage Vcc1; and

operating the second field programmable gate array structure at a second supply voltage Vcc2, Vcc1 being greater than Vcc2, effective transistor size A being smaller than effective transistor size B, the net driver in the first field programmable gate array structure being substantially identical to the net driver in the second field programmable gate array structure but for differences in a single interconnect layer.

27. The method of claim 26, wherein the single interconnect layer is a metal layer.

28. The method of claim 26, wherein the net driver of the first field programmable gate array outputs a first operating current during the operating at supply voltage Vcc1, and wherein the net driver of the second field programmable gate array outputs a second operating current during the operating at supply voltage Vcc2, the first and second operating currents being substantially equal.