Three-statable net driver for antifuse field programmable gate array
First Claim
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1. A programmable device, comprising:
- a logic module comprising;
an internal net driver having a first transistor and a second transistor, the first transistor having a source and drain of a first conductivity type, the second transistor having a source and a drain of a second conductivity type opposite the first conductivity type, the drain of the first transistor being coupled to the drain of the second transistor, the source and drain of the first transistor being disposed in a well, the source of the first transistor being coupled to a first supply voltage Vcc1, the source and drain of the second transistor not being disposed in the well;
a third transistor having a source and a drain of the first conductivity type, a gate electrode of the third transistor being coupled within the logic module to a DC voltage, the gate electrode of the third transistor not being coupled to gate electrode of the first transistor, the gate electrode of the third transistor not being coupled to a gate electrode of the second transistor, the source and drain of the third transistor being disposed in the well, the source of the third transistor being coupled to the first supply voltage Vcc1; and
a fourth transistor having a source and a drain of the second conductivity type, a gate electrode of the fourth transistor being coupled within the logic module to a second DC voltage, the gate electrode of the fourth transistor not being coupled to the gate electrode of the first transistor, the gate electrode of the fourth transistor not being coupled to the gate electrode of the second transistor, the source and drain of the fourth transistor not being disposed in the well;
wherein the source of the first transistor and the third transistor are not coupled to an optional second supply voltage Vcc2, the first supply voltage Vcc1 being greater than the second supply voltage Vcc2;
a first routing conductor coupled to the drain of the first transistor and to the drain of the second transistor;
a second routing conductor; and
an antifuse for coupling the first routing conductor to the second routing conductor, the first routing conductor, the second routing conductor and the antifuse being part of a programmable interconnect structure of the programmable device.
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Abstract
Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.
55 Citations
28 Claims
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1. A programmable device, comprising:
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a logic module comprising; an internal net driver having a first transistor and a second transistor, the first transistor having a source and drain of a first conductivity type, the second transistor having a source and a drain of a second conductivity type opposite the first conductivity type, the drain of the first transistor being coupled to the drain of the second transistor, the source and drain of the first transistor being disposed in a well, the source of the first transistor being coupled to a first supply voltage Vcc1, the source and drain of the second transistor not being disposed in the well; a third transistor having a source and a drain of the first conductivity type, a gate electrode of the third transistor being coupled within the logic module to a DC voltage, the gate electrode of the third transistor not being coupled to gate electrode of the first transistor, the gate electrode of the third transistor not being coupled to a gate electrode of the second transistor, the source and drain of the third transistor being disposed in the well, the source of the third transistor being coupled to the first supply voltage Vcc1; and a fourth transistor having a source and a drain of the second conductivity type, a gate electrode of the fourth transistor being coupled within the logic module to a second DC voltage, the gate electrode of the fourth transistor not being coupled to the gate electrode of the first transistor, the gate electrode of the fourth transistor not being coupled to the gate electrode of the second transistor, the source and drain of the fourth transistor not being disposed in the well; wherein the source of the first transistor and the third transistor are not coupled to an optional second supply voltage Vcc2, the first supply voltage Vcc1 being greater than the second supply voltage Vcc2; a first routing conductor coupled to the drain of the first transistor and to the drain of the second transistor; a second routing conductor; and an antifuse for coupling the first routing conductor to the second routing conductor, the first routing conductor, the second routing conductor and the antifuse being part of a programmable interconnect structure of the programmable device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A programmable device, comprising:
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a logic module comprising; an output driver having a first transistor and a second transistor, the first transistor having a source and drain of a first conductivity type, the second transistor having a source and drain of a second conductivity type opposite the first conductivity type, the drain of the first transistor being coupled to the drain of the second transistor, the source and drain of the first transistor being disposed in a well, the source and drain of the second transistor not being disposed in the well; a third transistor having a source and a drain of the first conductivity type, a gate electrode of the third transistor being coupled within the logic module to a DC voltage, the gate electrode of the third transistor not being coupled to gate electrode of the first transistor, the gate electrode of the third transistor not being coupled to a gate electrode of the second transistor, the source and drain of the third transistor being disposed in the well; and a fourth transistor having a source and a drain of the second conductivity type, a gate electrode of the fourth transistor being coupled within the logic module to a second DC voltage, the gate electrode of the fourth transistor not being coupled to the gate electrode of the first transistor, the gate electrode of the fourth transistor not being coupled to the gate electrode of the second transistor, the source and drain of the fourth transistor not being disposed in the well; a first routine conductor coupled to the drain of the first transistor and to the drain of the second transistor; a second routing conductor; and an antifuse for coupling the first routing conductor to the second routing conductor, the antifuse being a programmed antifuse which has a maximum permissible operating current, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at a first supply voltage Vcc1, the peak operating current flowing through the programmed antifuse being less than the maximum permissible operating current, wherein had the third transistor been coupled in parallel with the first transistor and had the fourth transistor been coupled in parallel with the second transistor, a peak operating current flowing through the programmed antifuse during switching of the first routing conductor during normal operation at the first supply voltage Vcc1 would be greater than the maximum permissible operating current. - View Dependent Claims (17, 18)
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19. A field programmable gate array, comprising:
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a programmable interconnect structure comprising routing conductors and antifuses, the antifuses having a maximum permissible operating current; and means for driving a net in the programmable interconnect structure at a first supply voltage Vcc1 using a first transistor and second transistor coupled in parallel so that the peak operating current flowing through the antifuses is less than the maximum permissible operating current if a first mask option is used, and for driving the net at a second supply voltage Vcc2 with the first transistor and without the second transistor so that the peak operating current flowing through the antifuses is less than the maximum permissible operating current if a second mask option is used, wherein the first supply voltage Vcc1 is less than the second supply voltage Vcc2. - View Dependent Claims (20, 21, 22)
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23. A method, comprising:
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using a first mask option to provide an effective pulldown transistor size A of a net driver in a first field programmable gate array structure having antifuses; using a second mask option to provide an effective pulldown transistor size B of a net driver in a second field programmable gate array structure having antifuses; operating the first field programmable gate array structure at a first supply voltage Vcc1; and operating the second field programmable gate array structure at a second supply voltage Vcc2, Vcc1 being greater than Vcc2, effective transistor size A being smaller than effective transistor size B, the net driver in the first field programmable gate array structure being substantially identical to the net driver in the second field programmable gate array structure but for differences in a single interconnect layer. - View Dependent Claims (24, 25)
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26. A method, comprising:
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using a first mask option to provide an effective pullup transistor size A of a net driver in a first field programmable gate array structure having antifuses; using a second mask option to provide an effective pullup transistor size B of a net driver in a second field programmable gate array structure having antifuses; operating the first field programmable gate array structure at a first supply voltage Vcc1; and operating the second field programmable gate array structure at a second supply voltage Vcc2, Vcc1 being greater than Vcc2, effective transistor size A being smaller than effective transistor size B, the net driver in the first field programmable gate array structure being substantially identical to the net driver in the second field programmable gate array structure but for differences in a single interconnect layer. - View Dependent Claims (27, 28)
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Specification