FPGA having predictable open-drain drive mode
First Claim
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1. A field-programmable gate array comprising a plurality of programmable cells, wherein:
- a first subset of the plurality of programmable cells are logic cells;
a second subset of the plurality of programmable cells are input/output (I/O) cells;
at least one of the plurality of programmable cells comprises one or more cell output nodes and an output node circuit for each of the cell output nodes;
at least one output node circuit comprises;
(a) an internal output data node;
(b) an output buffer having (1) a data-in port connected directly to the output data node, (2) a tri-state port, and (3) a data-out port, and adapted to receive (i) an output data signal at the data-in port directly from the output data node and (ii) a tri-state signal at the tri-state port and to generate an output signal at the data-out port for the cell output node; and
(c) a mux having two mux input ports, one of which is connected directly to the output data node, and a mux output port connected directly to the tri-state port of the output buffer and adapted to receive (i) the output data signal directly from the output data node and (ii) the tri-state signal at the two mux input ports and to generate at the mux output port a signal to be transmitted directly to the tri-state port of the output buffer to provide a dedicated path for the output data signal to be transmitted from the output data node to the tri-state port without passing through any other intervening logic in order to configure the output node circuit in an open-drain drive mode.
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Abstract
A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA'"'"'s general routing resources.
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12 Claims
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1. A field-programmable gate array comprising a plurality of programmable cells, wherein:
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a first subset of the plurality of programmable cells are logic cells; a second subset of the plurality of programmable cells are input/output (I/O) cells; at least one of the plurality of programmable cells comprises one or more cell output nodes and an output node circuit for each of the cell output nodes; at least one output node circuit comprises; (a) an internal output data node; (b) an output buffer having (1) a data-in port connected directly to the output data node, (2) a tri-state port, and (3) a data-out port, and adapted to receive (i) an output data signal at the data-in port directly from the output data node and (ii) a tri-state signal at the tri-state port and to generate an output signal at the data-out port for the cell output node; and (c) a mux having two mux input ports, one of which is connected directly to the output data node, and a mux output port connected directly to the tri-state port of the output buffer and adapted to receive (i) the output data signal directly from the output data node and (ii) the tri-state signal at the two mux input ports and to generate at the mux output port a signal to be transmitted directly to the tri-state port of the output buffer to provide a dedicated path for the output data signal to be transmitted from the output data node to the tri-state port without passing through any other intervening logic in order to configure the output node circuit in an open-drain drive mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification