Tunable delay for very high speed
First Claim
1. A continuously adjustable delay circuit, the circuit comprising:
- a first variable delay path circuit configured to receive a clock signal and a delay control signal, wherein the first variable delay path is operable to delay the clock signal by a first variable time interval that is inversely related to the delay control signal in order to generate a first delayed clock signal;
a second variable delay path circuit configured to receive the clock signal and the delay control signal, wherein the second variable delay path is operable to delay the clock signal by the first variable time interval that is directly related to the delay control signal in a complementary manner to the delay of the first variable delay path circuit in order to generate a second delayed clock signal; and
a selector circuit configured to receive the first and second delayed clock signals and being operable to select one of the first and second delayed clock signals for output as a data clock signal.
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Abstract
A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.
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Citations
21 Claims
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1. A continuously adjustable delay circuit, the circuit comprising:
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a first variable delay path circuit configured to receive a clock signal and a delay control signal, wherein the first variable delay path is operable to delay the clock signal by a first variable time interval that is inversely related to the delay control signal in order to generate a first delayed clock signal; a second variable delay path circuit configured to receive the clock signal and the delay control signal, wherein the second variable delay path is operable to delay the clock signal by the first variable time interval that is directly related to the delay control signal in a complementary manner to the delay of the first variable delay path circuit in order to generate a second delayed clock signal; and a selector circuit configured to receive the first and second delayed clock signals and being operable to select one of the first and second delayed clock signals for output as a data clock signal. - View Dependent Claims (2, 3, 4)
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5. A method for continuously adjusting a delay of a data clock signal, the method comprising the steps:
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delaying a reference clock signal by a first variable time interval that is inversely related to a control signal in order to produce a first delayed clock signal; delaying the reference clock signal by a second variable time interval that is directly related to the control signal in order to produce a second delayed clock signal; selecting one of the first and second delayed clock signals for output as a recovered data clock; comparing a phase of data transitions in a received data signal with a phase of the recovered data clock to determine a phase difference; and adjusting the control signal responsive to the phase difference. - View Dependent Claims (6, 7)
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8. A continuously adjustable delay-lock loop circuit, the circuit comprising:
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a first variable delay path circuit having inputs to receive a clock signal and a delay control signal, for controllably delaying the clock signal by a first variable time interval that is inversely related to the delay control signal, in order to generate a first delayed clock signal, wherein the first variable delay path circuit includes a first series of fixed delay elements coupled together in series with one another for delaying the clock signal; a second variable delay path circuit having inputs to receive the clock signal and the delay control signal, wherein the second variable delay path is operable to delay the clock signal by a second variable time interval that is directly related to the delay control signal in order to generate a second delayed clock signal wherein, the second variable delay path circuit includes a second series of fixed delay elements coupled together in series with one another for delaying the clock signal; and
the first and second variable delay paths include switches responsive to the delay control signal for selectively bypassing one or more of the fixed delay elements in each of the first and second variable delay paths so as to adjust the first and second time intervals in a complementary manner in response to the delay control signal; anda path selector for selecting one at a time of the first and second delayed clock signals for output as a recovered clock signal. - View Dependent Claims (9)
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10. A serial data clock recovery circuit for recovering a clock signal and serial data from a received data signal, comprising:
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a delay-locked loop circuit for controllably delaying a master clock input signal so as to form the recovered clock signal; the delay-locked loop circuit including a continuously adjustable delay circuit for adjusting a phase of the recovered clock signal so as to maintain synchrony with the received data signal;
whereinthe continuously adjustable delay circuit includes first and second complementary delay paths, the delay paths configured to delay the master clock input signal in a manner directly responsive to an applied tuning signal, and in a manner inversely responsive to the same tuning signal, respectively, so as to form first and second delayed clock signals, respectively, and further including a path selector circuit for selecting one at a time of the first and second delayed clock signals for output as the recovered clock signal. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method for recovering a data clock signal from a serial data receive signal, the method comprising the steps of:
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receiving a master clock signal having a predetermined frequency substantially equal to an expected frequency of the serial data receive signal; delaying the master clock signal by a first variable time interval so as to form a first delayed clock signal; delaying the master clock signal by a second variable time interval so as to form a second delayed clock signal; selecting at a time one of the first and second delayed clock signals for output as a recovered data clock; and synchronizing the recovered data clock to the serial data receive signal. - View Dependent Claims (17, 18, 19, 20)
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21. A serial data communications system comprising:
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one or more serial data communications channels, each channel including a transmitter and a receiver for transmitting and receiving serial data signals, respectively, the receiver including a serial data recovery circuit for recovering a clock signal and serial data from the corresponding received data signal; the serial data recovery circuit including a delay-locked loop circuit for controllably delaying a master clock input signal so as to maintain the recovered clock signal in synchrony with the received data signal; the delay-locked loop circuit including first and second complementary delay path circuits each delaying the master clock input signal so as to form first and second delayed clock signals, respectively; and further including a path selector circuit for selecting one at a time of the first and second delayed clock signals responsive to a select control signal for output as the recovered clock signal.
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Specification