Power amplification apparatus and method therefor

• US 6,028,485 A
• Filed: 08/03/1998
• Issued: 02/22/2000
• Est. Priority Date: 08/03/1998
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Myers, Ronald Gene, Sigmon, Bernard Eugene
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US09/128,600
• Time in Patent Office: 568 Days
• Field of Search: 330/124 R, 330/295, 330/302, 330/286, 333/116, 333/128, 333/161
• US Class Current: 330/295
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers

Abstract

A method and apparatus for efficiently amplifying input signals includes multiple amplifiers (20, 30). Each amplifier receives a signal from a power divider (12) where the input signal is split with substantially equal phase. Each amplifier drives a load (40) through a parallel coupled line pair (26, 36). The parallel coupled line pairs are preferably implemented in micro-strip or strip line technology. Each amplifier includes gate bias inputs (24, 34) and drain bias inputs (22, 32). The gate bias inputs can be biased equally and the drain bias inputs can be biased equally, resulting in a parallel, power combined, amplifier configuration. Alternately, the drain bias inputs can be staggered, or the gate bias inputs can be staggered to increase efficiency.

Claims

1. An amplifier circuit comprising:

an input and an output;

a first amplifier having a first gate bias, a first drain bias, a first signal input coupled to the input of the amplifier circuit, and a first signal output, said first amplifier comprising means for amplifying a lower power portion of a signal;

a second amplifier having a second gate bias, a second drain bias, a second signal input coupled to the input of the amplifier circuit, and a second signal output, said second amplifier comprising means for amplifying a higher power portion of said signal;

a first impedance inverter coupled between the first output of the first amplifier and the output of the amplifier circuit; and

a second impedance inverter coupled between the second output of the second amplifier and the output of the amplifier circuit.

2. The amplifier circuit of claim 1 wherein the first impedance inverter comprises parallel coupled line sections, and the second impedance inverter comprises parallel coupled line sections.

3. The amplifier circuit of claim 2 wherein:

said first gate bias and said second gate bias are biased substantially the same;

the first drain bias is set to a first voltage; and

the second drain bias is set to a second voltage, wherein the first voltage and the second voltage are not the same voltage.

4. The amplifier circuit of claim 2 wherein:

said first gate bias and said second gate bias are biased differently;

the first drain bias is set to a first voltage; and

the second drain bias is set to a second voltage, wherein the first voltage and the second voltage are substantially the same voltage.

5. The amplifier circuit of claim 2 wherein:

said first gate bias and said second gate bias are biased substantially the same;

the first drain bias is set to a first voltage; and

the second drain bias is set to a second voltage, wherein the first voltage and the second voltage are substantially the same voltage.

6. The amplifier circuit of claim 2 further comprising a power divider coupled between the input of the amplifier and the first input of the first amplifier, and coupled between the input of the amplifier circuit and the second input of the second amplifier, wherein the power divider divides an input signal present at the input of the amplifier circuit into two signals having substantially the same phase.

7. An amplifier circuit comprising:

an input and an output;

a first amplifier having a first gate bias, a first drain bias, a first signal input coupled to the input of the amplifier circuit, and a first signal output;

a second amplifier having a second gate bias, a second drain bias, a second signal input coupled to the input of the amplifier circuit, and a second signal output;

a third amplifier having a third gate bias, a third drain bias, a third signal input coupled to the input of the amplifier circuit, and a third signal output;

a fourth amplifier having a fourth gate bias, a fourth drain bias, a fourth signal input coupled to the input of the amplifier circuit, and a fourth signal output;

a first impedance inverter coupled between the first output of the first amplifier and the output of the amplifier circuit;

a second impedance inverter coupled between the second output of the second amplifier and the output of the amplifier circuit;

a third impedance inverter coupled between the third output of the third amplifier and the output of the amplifier circuit; and

a fourth impedance inverter coupled between the fourth output of the fourth amplifier and the output of the amplifier circuit.

8. The amplifier circuit of claim 7 wherein the first impedance inverter comprises parallel coupled line sections, the second impedance inverter comprises parallel coupled line sections, the third impedance inverter comprises parallel coupled line sections, and the fourth impedance inverter comprises parallel coupled line sections.

9. The amplifier circuit of claim 8 wherein:

said first gate bias, said second gate bias, said third gate bias, and said fourth gate bias are biased substantially the same.

10. The amplifier of claim 9 wherein the first amplifier and the second amplifier are carrier amplifiers, the third amplifier and the fourth amplifier are peaking amplifiers, and the drain biases of the peaking amplifiers are set to higher voltages than the drain biases of the carrier amplifiers.

11. The amplifier of claim 10 wherein:

the drain biases of the carrier amplifiers are set to different voltages; and

the drain biases of the peaking amplifiers are set to substantially the same voltage.

12. The amplifier of claim 10 wherein:

the drain biases of the peaking amplifiers are set to different voltages; and

the drain biases of the carrier amplifiers are set to substantially the same voltage.

13. The amplifier of claim 10 wherein:

the drain biases of the carrier amplifiers are set to substantially the same voltage; and

the drain biases of the peaking amplifiers are set to substantially the same voltage.

14. The amplifier of claim 9 wherein the first drain bias, the second drain bias, the third drain bias, and the fourth drain bias are all set to substantially the same voltage.

15. The amplifier of claim 8 wherein the first drain bias, the second drain bias, the third drain bias, and the fourth drain bias are all set to substantially the same voltage.

16. The amplifier of claim 15 wherein the first amplifier and the second amplifier are carrier amplifiers, the third amplifier and the fourth amplifier are peaking amplifiers, and the gate biases of the peaking amplifiers are set to voltages different than the gate biases of the carrier amplifiers such that the peaking amplifiers turn on at higher input signal power levels than the carrier amplifiers.

17. The amplifier of claim 16 wherein:

the gate biases of the carrier amplifiers are biased differently; and

the gate biases of the peaking amplifiers are biased substantially the same.

18. The amplifier of claim 16 wherein:

the gate biases of the peaking amplifiers are biased differently; and

the gate biases of the carrier amplifiers are biased substantially the same.

19. The amplifier of claim 16 wherein:

the gate biases of the carrier amplifiers are biased substantially the same; and

the gate biases of the peaking amplifiers are biased substantially the same.

20. A method of amplifying an input signal, said method comprising the steps of:

amplifying a first portion of said input signal with a first amplifier having a first drain bias, thereby producing a first amplified signal;

phase shifting the first amplified signal with a first parallel coupled line, thereby producing a first phase shifted signal;

amplifying a second portion of said input signal with a second amplifier having a second drain bias, wherein the second drain bias is set to a higher voltage than the first drain bias, thereby producing a second amplified signal;

phase shifting the second amplified signal with a second parallel coupled line, thereby producing a second phase shifted signal; and

combining the first phase shifted signal and the second phase shifted signal to produce an amplified replica of the input signal.