Liquid crystal display device

• US 6,028,580 A
• Filed: 09/25/1996
• Issued: 02/22/2000
• Est. Priority Date: 09/28/1995
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kosegawa, Seishi, Takafuji, Yutaka, Yamashita, Toshihiro
• Primary Examiner(s): Luu, Matthew
• Assistant Examiner(s): PIZIALI, JEFFREY J
• Application Number:
  US08/719,442
• Time in Patent Office: 1,245 Days
• Field of Search: 257/72, 257/341, 257/350, 359/59, 350/150, 340/752, 340/784, 357/23.7, 438/199, 345/98
• US Class Current: 345/98
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A driving circuit integrated type active-matrix liquid crystal display device is arranged such that a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series is adopted for the P-channel thin film transistor and an N-channel thin film transistor; at least one of the P-channel thin film transistor and the N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel; and at least one of a power source line and an output line connected to the plurality of thin film transistors connected in parallel is formed in a wiring pattern composed of a main wiring section and a branched wiring section branched into respective thin film transistors. The described arrangement permits a line-shaped defect due to a defective thin film transistor which constitutes a buffer of the drive circuit to be eliminated with ease, while improving a yield of panels.

Claims

1. A liquid crystal display device provided with a driving circuit deposited on a substrate having formed thereon a plurality of display pixel sections, said driving circuit being provided for driving the display pixel sections, wherein:

said driving circuit includes a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series,

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel between a power source line and an output line, and

at least one of said power source line and said output line is formed in a wiring pattern composed of a main wiring section and branched wiring sections branched into respective thin film transistors, so that when any of said plurality of thin film transistors connected in parallel becomes defective, a thin film transistor which has become defective is alone disconnectable from one of said power source line and said output line.

2. The liquid crystal display device as set forth in claim 1, wherein:

said thin film transistors connected to the branched wiring sections each include a contact for connecting a branched wiring section and a semiconductor layer, and

said branched wiring sections are disposed between said main wiring section and a contact.

3. The liquid crystal display device as set forth in claim 1, wherein:

a gate line connected to said buffer includes gate electrode sections disposed in said thin film transistors and intermediate wiring sections for connecting between gate electrode sections of said thin film transistors, and

said intermediate wiring sections are composed of a thin film layer that is different from a thin film layer adopted in said gate electrode sections, and are connected to the gate electrode sections via through holes in a vicinity of main bodies of said thin film transistors.

4. The liquid crystal display device as set forth in claim 2, wherein:

a gate line connected to said buffer includes gate electrode sections disposed in said thin film transistors and intermediate wiring sections for connecting between gate electrode sections of said thin film transistors, and

said intermediate wiring sections are composed of a thin film layer that is different from a thin film layer adopted in said gate electrode sections, and the thin film layer of said intermediate wiring sections are in contact with the thin film layer of said gate electrode sections in a vicinity of main bodies of said thin film transistors, with a contact surface therebetween parallel to said surface.

5. The liquid crystal display device as set forth in claim 1, wherein:

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of at least three thin film transistors connected in parallel, and

among said at least three thin film transistors, thin film transistors disposed at end sides have a channel width smaller than a channel width of other thin film transistors.

6. The liquid crystal display device as set forth in claim 1, wherein:

said P-channel thin film transistor has a source connected to a high potential power source, a gate to which a signal from a shift register is input and a drain from which a signal for driving a pixel display section is output, and

said N-channel thin film transistor has a source connected to a low potential power source, a gate to which a signal is input from a shift register and a drain from which a signal for driving a pixel display section is output.

7. The liquid crystal display device as set forth in claim 1, wherein:

said branched wiring sections have a width in a range of from 2 μ

m to 1/2 of a channel width of said thin film transistors to which said branched wiring sections are connected.

8. A liquid crystal display device provided with a driving circuit deposited on a substrate having formed thereon a plurality of display pixel sections, said driving circuit being provided for driving the display pixel sections, wherein:

said driving circuit includes a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series,

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel between a power source line and an output line,

said plurality of thin film transistors connected in parallel respectively include a plurality of gates said plurality of gates being interconnected through a gate line, and

said gate line is formed in a wiring pattern composed of divided wiring sections that are divided for respective gates and a connecting wiring section for connecting respective divided wiring sections provided between respective thin film transistors, so that when a gate of any of said plurality of thin film transistors connected in parallel becomes defective, a gate which has become defective is alone disconnectable from said gate line.

9. The liquid crystal display device as set forth in claim 8, wherein:

said gate line connected to said buffer includes gate electrode sections disposed in said thin film transistors and intermediate wiring sections for connecting between said gate electrode sections of said thin film transistors, and

said intermediate wiring sections are composed of a thin film layer that is different from a thin film layer adopted in said gate electrode sections, and the thin film layer of said intermediate wiring sections are in contact with the thin film layer of said gate electrode sections in a vicinity of main bodies of said thin film transistors, with a contact surface therebetween parallel to said substrate.

10. The liquid crystal display device as set forth in claim 8, wherein:

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of at least three thin film transistors connected in parallel, and

among said at least three thin film transistors, thin film transistors disposed at end sides have a channel width smaller than a channel width of other thin film transistors.

11. The liquid crystal display device as set forth in claim 8, wherein:

said P-channel thin film transistor has a source connected to a high potential power source through a first power source line, a gate to which a signal from a shift register is input through said gate line and a drain from which a signal for driving a pixel display section is output through said output line, and

said N-channel thin film transistor has a source connected to a low potential power source through a second power source line, a gate to which a signal is input from a shift register through said gate line and a drain from which a signal for driving a pixel display section is output through said output line.

12. A liquid crystal display device provided with a driving circuit deposited on a substrate having formed thereon a plurality of display pixel sections, said driving circuit being provided for driving the display pixel sections, wherein:

said driving circuit includes a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series,

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel between a power source line and an output line,

said plurality of thin film transistors connected in parallel respectively include a plurality of gates, said plurality of gates being interconnected through a gate line, and

said gate line for connecting said plurality of gates is formed in a wiring pattern composed of divided wiring sections that are divided for respective gates and a connecting wiring section for connecting respective terminal ends of the divided wiring sections, so that when a gate of any of said plurality of thin film transistors connected in parallel becomes defective, a gate which has become defective is alone disconnectable from said gate line.

13. The liquid crystal display device as set forth in claim 12, wherein:

said gate line connected to said buffer includes gate electrode sections disposed in said thin film transistors and intermediate wiring sections for connecting between said gate electrode sections of said thin film transistors, and

said intermediate wiring sections are composed of a thin film layer that is different from a thin film layer adopted in said gate electrode sections, and the thin film layer of said intermediate wiring sections are in contact with the thin film layer of said gate electrode sections in a vicinity of main bodies of said thin film transistors, with a contact surface therebetween parallel to said substrate.

14. The liquid crystal display device as set forth in claim 12, wherein:

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of at least three thin film transistors connected in parallel, and

among said at least three thin film transistors, thin film transistors disposed at end sides have a channel width smaller than a channel width of other thin film transistors.

15. The liquid crystal display device as set forth in claim 12, wherein:

said P-channel thin film transistor has a source connected to a high potential power source through a first power source line, a gate to which a signal from a shift register is input through said gate line and a drain from which a signal for driving a pixel display section is output through said output line, and

said N-channel thin film transistor has a source connected to a low potential power source through a second power source line, a gate to which a signal is input from a shift register through said gate line and a drain from which a signal for driving a pixel display section is output through said output line.

16. A liquid crystal display device provided with a driving circuit deposited on a substrate having formed thereon a plurality of display pixel sections, said driving circuit being provided for driving the display pixel sections, wherein:

said driving circuit includes a buffer composed of a P-channel thin film transistor and an N-channel thin film transistor that are connected in series,

at least one of said P-channel thin film transistor and said N-channel thin film transistor is composed of a plurality of thin film transistors that are connected in parallel between a power source line and an output line,

said plurality of thin film transistors connected in parallel are formed by a plurality of semiconductor pieces that are formed in one integral part, and

at least one of said power source line, said output line and a gate line is formed in a wiring pattern composed of a main wiring section and a branched wiring section branched into respective thin film transistors from the main wiring section, so that when any of said plurality of thin film transistors connected in parallel becomes defective, a thin film transistor which has become defective is alone disconnectable from one of said power source line, said output line and said gate line.

17. The liquid crystal display device as set forth in claim 16, wherein:

said thin film transistors connected to the branched wiring section each include a contact for connecting the branched wiring section and a semiconductor layer, and

said branched wiring section is disposed between said main wiring section and to a contact.

18. The liquid crystal display device as set forth in claim 16, wherein:

a gate line connected to said buffer includes gate electrode sections disposed in said thin film transistors and intermediate wiring sections for connecting between gate electrode sections of said thin film transistors, and

said intermediate wiring sections are composed of a thin film layer that is different from a thin film layer adopted in said gate electrode sections, and the thin film layer of said intermediate wiring sections are in contact with the thin film layer of said gate electrode sections in a vicinity of main bodies of said thin film transistors, with a contact surface therebetween parallel to said substrate.

19. The liquid crystal display device as set forth in claim 16, wherein:

said P-channel thin film transistor has a source connected to a high potential power source through a first power source line, a gate to which a signal from a shift register is input through said gate line and a drain from which a signal for driving a pixel display section is output through said output line, and

said N-channel thin film transistor has a source connected to a low potential power source through a second power source line, a gate to which a signal is input from a shift register through said gate line and a drain from which a signal for driving a pixel display section is output through said output line.