Power factor correction converter

• US 6,028,776 A
• Filed: 11/24/1997
• Issued: 02/22/2000
• Est. Priority Date: 07/31/1997
• Status: Expired due to Term

• Current Assignee: Solum Co., Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ji, Ho Kyun, Cho, Bo Hyung, Lee, Kyu Chan
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US08/976,545
• Time in Patent Office: 820 Days
• Field of Search: 363/15, 363/16, 363/20, 363/21, 363/95, 363/97, 363/131
• US Class Current: 363/21.05
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A PFC converter includes a bridge diode, a booster section controlled for improving a power factor of the bridge diode, a transformer section supplied with an output of the booster section via a primary coil side to excite it to a secondary coil side, a switch section for switching the output of the booster section, an output section for rectifying and smoothing the output of secondary coil side of the transformer section, a control section for sensing to feedback an output voltage of the output section and thus control the switch section, and a delay section operated for applying a stable voltage to the transformer section by controlling the booster section according to the output of the control section, so that the booster section is controlled for decreasing the harmonic current by the delayed output of the delay section to constantly maintain the voltage of a bulk condenser and thereby improve the power factor while controlling double stage PFC converter and DC--DC converter by the single phase.

Claims

1. A PFC converter comprising:

a booster section for switching an output of a bridge diode section for rectifying an input voltage for generating a stable output voltage;

a switch section for switching the output of said booster section to a primary coil side of a transformer section;

an output section for rectifying and smoothing an output of a secondary coil side of said transformer section;

a control section for sensing an output voltage of said output section and performing a feedback operation of a sensing signal to said switch section to control an output of said output section;

a booster control section having a first means for increasing a high level interval of an output pulse of a comparator in the control section by a preset time period and a second means for variably decreasing the high level interval of the output pulse in the first means within a range of a preset time period, and operating power factor to be improved by maintaining said output of said booster section uniformly,

wherein said first means comprises a first buffer section including a first NAND gate for inverting the pulse of the comparator in the control section; and

a second buffer section including a first delay section for delaying the output pulse of the first buffer section for a predetermined time period and outputting a resultant value, and a second NAND gate for NANDing an output pulse of the first delay section and the output pulse of the first buffer section, and

the second means comprises an amplifying section for amplifying an output signal of an OP amplifier of the control section;

a third buffer section including a second delay section for variably delaying the output pulse of the second buffer section in accordance with the output signal of the amplifying section, and a third NAND gate for NANDing the output pulse of the second delay section and the output pulse of the second buffer section; and

a fourth buffer section including a fourth NAND gate for inverting the output pulse of the third buffer section.

2. A PFC converter in accordance with claim 1, wherein the first delay section comprises:

a first resistance connected between an output terminal of the second buffer section ad an input terminal of the second NAND gate; and

a first condenser having an end thereof connected to a common node of the first resistance and the second NAND gate and another end thereof connected to ground.

3. A PFC converter in accordance with claim 1, wherein the second delay section comprises:

a second resistance connected between an output terminal of the second NAND gate and an input terminal of the third NAND gate;

a third resistance having an end thereof connected to a common node of the output terminal of the second NAND gate and the second resistance;

a second switching device having a collector connected to another end of the third resistance, a base connected to an output terminal of the amplifying section, and an emitter connected to a common node of the second resistance and the second switching device; and

a second condenser having an end thereof connected to a common node of the emitter of the second switching device and the third NAND gate, and another end thereof connected to ground.