Flash memory device

• US 6,028,788 A
• Filed: 09/02/1997
• Issued: 02/22/2000
• Est. Priority Date: 08/30/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jeong-hyuk, Shin, Wang-chul
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/922,047
• Time in Patent Office: 903 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.33
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A flash memory device for providing high integration and high-speed data access has string blocks arranged in a two-dimensional manner. Each string block has a plurality of strings, at least one bit line select line, a plurality of word lines, a plurality of source line select lines, a first dual-mode line, and a second dual-mode line. Each string is constructed such that at least one bit line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are connected in series. The bit line select lines are connected to respective gates of the bit line select transistors. The plurality of word lines are connected to respective control gates of the plurality of unit memory cells. The first dual-mode line is connected to one end of each of the strings in a first string block through a bit line contact, and the second dual-mode line is connected to other end of each of the strings in the first string block through a source line contact. Additionally, the first dual-mode line is connected to the source line contact of a second string block while the second dual-mode line is connected to the bit line contact of a third string block.

Claims

1. A flash memory device having a first, a second, and a third string block arranged in a two-dimensional manner for constructing a memory cell array, each string block having a bit line contact and a source line contact, the flash memory device comprising:

a plurality of strings within each string block, each string having a first end and a second end;

a bit line select transistor having a gate disposed along each string;

a plurality of memory cells disposed along each string, each memory cell having a control gate;

a plurality of source line select transistors disposed along each string, each source line select transistor having a gate, the bit line select transistor, the unit memory cells and the source line select transistors being connected to each other in series;

a bit line select line being connected to the gate of the bit line select transistor;

a plurality of word lines, each word line being connected to the control gate of one of the memory cells in each string;

a plurality of source line select lines, each source line select line being connected to the gate of one of the source line select transistors in each string;

a first dual-mode line being connected to the first end of each of the strings in the first string block through the bit line contact thereof and being further connected to the source line contact of the second string block; and

a second dual-mode line being connected to the second end of each of the strings in the first string block through the source line contact thereof and being further connected to the bit line contact of the third string block.

2. The flash memory device as claimed in claim 1, wherein the bit line select transistor comprises a plurality of bit line select transistors serially connected, each bit line select transistor having a threshold voltage different from the other(s).

3. The flash memory device as claimed in claim 1, wherein the plurality of source line select transistors are serially connected, each having a threshold voltage different from one another.

4. The flash memory device as claimed in claim 1, wherein the first dual-mode line operates as a source line when the second dual-mode line operates as a bit line, and vice-versa.

5. The flash memory device as claimed in claim 1, wherein a bipolar transistor having a base, an emitter, and a collector is formed in the bit line contact of each of the string blocks.

6. The flash memory device as claimed in claim 5, wherein the bipolar transistor is of a PNP type.

7. The flash memory device as claimed in claim 5, wherein the base of the bipolar transistor is connected to the line select transistor, the emitter of the bipolar transistor is connected to the first dual-mode line, and the collector of the bipolar transistor is connected to a P-type bulk substrate, in which the respective strings are formed.

8. The flash memory device as claimed in claim 5, wherein the impurity of a base region of the bipolar transistor is of the same type as that of a region where the source line contact is formed.

9. The flash memory device as claimed in claim 7, wherein a concentration of a base region of the bipolar transistor is lower than that of a source or drain of the unit memory cell.

10. A method of performing a program operation of a flash memory device comprising a plurality of dual-mode lines, a bit line select line, a plurality of word lines, a plurality of string blocks, and a plurality of strings in each of the string blocks, each string comprising a plurality of unit memory cells, the method comprising:

selecting one of the unit memory cells of a selected one of the strings to be programmed;

operating a first one of the dual-mode lines as as a bit line and a second one of the dual-mode lines as a source line;

applying a supply voltage to each of the dual-mode lines, to the bit line select line, and to the source line select lines;

applying a pass voltage higher than or equal to the supply voltage and lower than a program voltage to each of the word lines for a predetermined time, so that a channel region of each of the unit memory cells is precharged;

continuously applying a program voltage of about 18V to a selected word line among the plurality of word lines, while continuously applying the voltage to non-selected ones of the word lines, thereby self-boosting the channel region of the selected memory cell over a precharge voltage and preventing non-selected ones of the unit memory cells from being programmed; and

discharging a channel voltage of each of the non-selected ones of the unit memory cells of the selected string by connecting only the selected string to the source line.

11. A method of performing a read operation of a flash memory device comprising a plurality of word lines, a plurality of dual-mode lines, a bit line select line, a plurality of source line select lines, a plurality of string blocks, and a plurality of strings in each of the string blocks, each string comprising a plurality of unit memory cells, the method comprising:

selecting one of the unit memory cells in a selected one of the strings connected to a selected one of the word lines to be read;

applying a supply voltage to the bit line select line, to a second one of the source line select lines, and to non-selected ones of the word lines;

applying a voltage of about 1.5V to one of the dual mode lines acting as a bit line;

applying a ground voltage of about 0V to one of the dual-mode lines acting as a source line, to the selected one of the word lines, and to a first one of the source line select lines, such that a cell current flows through the dual-mode line acting as the source line when the selected unit memory cell has been erased but does not flow when the selected unit memory cell is programmed; and

detecting a voltage value of the dual-mode line acting as a bit line using a sense amplifier to read a cell data value.

12. The method of performing a read operation according to claim 11, in which each string block comprises a bit line contact in which a bipolar transistor having a base, an emitter, and a collector is formed, the method further comprising:

amplifying the cell current through the bipolar transistor.