Low power signal processing for spread spectrum receivers

• US 6,028,883 A
• Filed: 06/26/1997
• Issued: 02/22/2000
• Est. Priority Date: 07/12/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Harrison, Daniel David, Tiemann, Jerome Johnson
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): Tadesse, Binyam
• Application Number:
  US08/883,162
• Time in Patent Office: 971 Days
• Field of Search: 370/320, 370/335, 370/342, 370/350, 375/200, 375/206, 375/208, 375/209, 375/210, 342/357, 342/701
• US Class Current: 375/150
• CPC Class Codes: G01S 19/09 providing processing capability normally carried out by the receiver
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/42 Determining position
• CPC Class Codes: G01S 5/0027 of actual mobile position, i.e. position determined on mobile
• CPC Class Codes: G01S 5/0036 of measured values, i.e. measurement on mobile and position calculation on base station
• CPC Class Codes: G01S 5/0054 of actual mobile position, i.e. position calculation on base station
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 2201/70709 with discontinuous detection
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A direct sequence spread spectrum architecture permits low power consumption during a synchronization phase of data reception by allowing the receiver to be turned off during most of the acquisition phase of reception, or by using a parallel correlator to keep acquisition time short. The architecture is particularly suitable for global positioning satellite (GPS) signal processing and permits multiple satellite codes and multiple Doppler bins to be searched either sequentially, without requiring the receiver to be turned on during the search process. The receiver output baseband data is sampled and stored over a time interval sufficient to achieve acquisition and synchronization for any one code division multiple access (CDMA) signal at any specific Doppler shift. This sample is digitally recorded and re-played from memory as many times as may be required to acquire and synchronize each desired CDMA signal. To keep processing energy consumption low, an analog (capacitor-based) cross-correlator is used. The order of coherent and non-coherent processing for all code-Doppler channels is chosen to maximize energy efficiency while minimizing required processor hardware.

Claims

1. A direct sequence spread spectrum (DSSS) signal processing architecture including a receiver for receiving at least a time segment of code division multiple access (CDMA) signals that is sufficient to allow high-reliability acquisition of the signals, said architecture comprising:

a memory for storing receiver output data collected over said time segment;

means for turning off the receiver after said receiver output data has been stored in said memory;

means for reading said data from said memory;

a code/Doppler generator for providing a segment of a replica signal;

a correlator for measuring correlation between the replica segment and a segment of the receiver output data, said correlator being responsive to said receiver output data segment read from said memory and to said replica segment;

detection means responsive to said correlator for detecting a predetermined correlation level; and

sampling means for sampling receiver output baseband data at a non-integer oversampling rate so as to produce a sampling roll whereby an accurate correlation peak is obtained with minimal memory and a minimal sampling rate.

2. A direct sequence spread spectrum (DSSS) signal processing architecture including a receiver for receiving code division multiple access (CDMA) signals, said architecture comprising:

memory, means for storing a segment of receiver output data;

means for reading said data from said memory means;

a code/Doppler generator for providing a segment of a replica signal, said signal being defined in part by a replica code, code offset and Doppler frequency;

a parallel correlator for measuring correlation between said replica signal segment and a segment of the receiver output data, said correlator being responsive to said receiver output data segment read from said memory means and to said replica signal segment, said means for reading data from said memory means being adapted to deliver a segment of multiple data samples simultaneously to said correlator, and said code/Doppler generator being adapted to deliver a segment of multiple replica signal samples simultaneously to said correlator; and

detection means responsive to said correlator for determining a predetermined correlation level.

3. The DSSS signal processing architecture of claim 2 including means for changing the replica signal segment, wherein said detection means is adapted to determine the replica signal segment that yields highest correlation with the receiver output data.

4. The DSSS signal processing architecture of claim 2 including means for shifting one of said segment of replica signal and said data read from said memory means, relative to the other.

5. The DSSS signal processing architecture of claim 2 including means for turning off the receiver after said receiver output data has been stored in said memory.

6. The DSSS signal processing architecture of claim 2 wherein said memory means comprises elements to accept digital signal data written sequentially therein and to provide massively parallel output of data such that a sequence of data of predetermined length is available at the output of said memory means simultaneously, said code/Doppler generator further including a replica shift register comprising elements organized for massively parallel output of data having a data sequence length equal to the data sequence length provided by said memory means.

7. The DSSS signal processing architecture of claim 2 wherein said memory means comprises elements organized to accept digital data written sequentially therein and to provide massively parallel output of data such that a sequence of data of predetermined length is available at the output of said memory means simultaneously, said code/Doppler generator further including a Doppler register and a code register, said Doppler register and said code register comprising elements organized for massively parallel output of data having a data sequence length equal to the data sequence length provided by said memory means.

8. The DSSS signal processing architecture of claim 2 wherein said code/Doppler generator is adapted to program the generated segment of replica signal samples for different Doppler frequencies.

9. The DSSS signal processing architecture of claim 2 wherein the code/Doppler generator comprises:

replica register means for storing said replica segment and adapted to provide as an output signal said segment of multiple replica samples simultaneously.

10. The DSSS signal, processing architecture of claim 2 wherein the code/Doppler generator comprises:

a code replica register for storing a specific pseudo-random noise (P/N) code; and

a Doppler-replica register for storing a sampled digital representation of a properly phased sinusoid corresponding to a frequency bin under examination;

said replica code and said Doppler frequency within said replica signal segment being of equal sample length for presentation in parallel to said parallel correlator.

11. The DSSS signal processing architecture of claim 2 wherein the parallel correlator comprises:

an array of multipliers for developing products of samples of said data segment from said receiver output data memory means with corresponding samples of said replica segment; and

an analog summer for adding the output signals of said multipliers simultaneously.

12. The DSSS signal processing architecture of claim 10 wherein the parallel correlator comprises:

an array of multipliers for developing products of samples of said data segment from said receiver output data memory means with corresponding samples of said digital representation of said properly phased sinusoid and corresponding samples of said specific P/N code in said code replica register;

an array of digital-to-analog converters coupled to said array of multipliers for converting output signals from said array of multipliers to analog form; and

an analog adder for adding the output signals of said digital-to-analog converters simultaneously.

13. The DSSS signal processing architecture of claim 11 wherein each multiplier in said multiplier array is adapted to produce digital representations of the developed products, and wherein the analog summer comprises:

an array of digital-to-analog converters with each respective digital-to-analog converter coupled to a respective multiplier in said multiplier array; and

an analog adder for summing the output signals of said digital-to-analog converters simultaneously.

14. The DSSS signal processing architecture of claim 13 wherein each of said digital-to-analog converters comprises:

a plurality of capacitors for storing values of charge corresponding to the associated digital representation of a developed product; and

a plurality of switches, each respective one of said switches being adapted to supply to one side of a corresponding one of said capacitors a selected one of a positive voltage, negative voltage, and reference voltage in response to a three level bipolar digital representation of said developed product, the other side of each of said capacitors being coupled to a charge summation line common to all digital-to-analog converters in the array and comprising the analog adder.

15. The DSSS signal processing architecture of claim 14 wherein each of the capacitors is of substantially identical capacitance value.

16. The DSSS signal processing architecture of claim 14 wherein the multiplier array and digital-to-analog converter array are each differential, and wherein the analog adder is differential and adapted to generate both positive and negative summation results.

17. The DSSS signal processing architecture of claim 12 wherein each multiplier in said multiplier array is adapted to produce digital representations of the developed products and wherein the analog summer comprises:

an array of digital-to-analog converters with each respective digital-to-analog converter coupled to a respective multiplier in said multiplier array; and

an analog adder for summing the output signals of said digital-to-analog converters simultaneously.

18. The DSSS signal processing architecture of claim 2 including sampling means for sampling receiver output data at a non-integer oversampling rate so as to produce a sampling roll whereby an accurate correlation peak is obtained with minimal memory and register length.