Power saving scheme for a digital wireless communications terminal
First Claim
1. A clock circuit comprising:
- at least two asynchronous clock sources, includinga high accuracy clock source for maintaining a timebase in a first mode, anda low power clock source for maintaining the timebase in a second mode for a given time interval; and
a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source;
wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.
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Abstract
According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g., in a paging mode), a sleep mode is enabled wherein the high accuracy clock source is disabled, the DSP, CSP, and communications protocol processor are shut down, and the "slow clock" provides the timebase for the terminal while a sleep counter is decremented for a given sleep interval. Upon expiration of the sleep interval or in response to an intervening external event (e.g., a keypad is depressed), a terminal wake-up is initiated so that the high accuracy clock resumes control of the timebase. Because the high accuracy clock and the "slow clock" are not synchronized, the CSP and DSP calibrate the "slow clock" to the high accuracy clock prior to the terminal entering the sleep mode.
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Citations
40 Claims
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1. A clock circuit comprising:
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at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A cellular communications terminal, comprising:
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at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said conversion signal processor; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A power saving method, comprising the steps of:
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maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a programmable processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said accumulator. - View Dependent Claims (18, 19, 20)
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21. A method of operating a cellular communications terminal, comprising the steps of:
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maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a conversion signal processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator in said conversion signal processor according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship using a digital signal processor based on a resulting value in said accumulator. - View Dependent Claims (22, 23, 24)
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25. A clock circuit comprising:
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at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a digital device having a first register and a second register coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source. - View Dependent Claims (26, 27, 28, 29)
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30. A cellular communications terminal, comprising:
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at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a digital device having a first register and a second register, said digital device coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said digital device; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source. - View Dependent Claims (31, 32, 33, 34)
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35. A power saving method comprising the steps of:
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maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register. - View Dependent Claims (36, 37)
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38. A method of operating a cellular communications terminal, comprising the steps of:
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maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register. - View Dependent Claims (39, 40)
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Specification