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Power saving scheme for a digital wireless communications terminal

  • US 6,029,061 A
  • Filed: 03/11/1997
  • Issued: 02/22/2000
  • Est. Priority Date: 03/11/1997
  • Status: Expired due to Term
First Claim
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1. A clock circuit comprising:

  • at least two asynchronous clock sources, includinga high accuracy clock source for maintaining a timebase in a first mode, anda low power clock source for maintaining the timebase in a second mode for a given time interval; and

    a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source;

    wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.

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