Apparatus for reducing computer system power consumption
First Claim
1. An apparatus for use with a computer system for reducing power consumption of the computer system, comprising:
- a processor having a clocking input;
memory coupled to said processor;
means for producing a clocking signal having a frequency;
a counter coupled to said processor for counting a number of events indicative of activity of the computer system during a preset period of activity of said processor;
means coupled to said counter for periodically reading the number of events counted by said counter;
means coupled to said periodic reading means and said clocking signal producing means for adjusting the frequency of the clocking signal based on the counted number of events; and
means coupled to said adjusting means for outputting the frequency adjusted clocking signal to said processor clocking input.
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Accused Products
Abstract
A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.
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Citations
22 Claims
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1. An apparatus for use with a computer system for reducing power consumption of the computer system, comprising:
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a processor having a clocking input; memory coupled to said processor; means for producing a clocking signal having a frequency; a counter coupled to said processor for counting a number of events indicative of activity of the computer system during a preset period of activity of said processor; means coupled to said counter for periodically reading the number of events counted by said counter; means coupled to said periodic reading means and said clocking signal producing means for adjusting the frequency of the clocking signal based on the counted number of events; and means coupled to said adjusting means for outputting the frequency adjusted clocking signal to said processor clocking input. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for reducing power consumption of a computer system, the system including a processor and a clocking signal producer having a clocking signal frequency, comprising the steps of:
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counting a number of events indicative of the activity level of the computer system during a preset period; periodically determining counted number of events; adjusting the frequency of the clocking signal from the clocking signal producer based on the counted number of events; and outputting the frequency adjusted clocking signal to the processor. - View Dependent Claims (8, 9, 10, 11, 12)
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13. An apparatus for use with a computer system for reducing power consumption of the computer system, comprising:
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a processor having a clocking input; means for producing a clocking signal having a frequency; cache memory coupled to said processor; main memory coupled to said processor, and having a main memory cycle is performed during write operations and cache read miss operations; a counter coupled to said processor and said main memory for counting a number of main memory cycles; means coupled to said counter and said processor for periodically reading said counter to determine the counted number of main memory cycles; means coupled to said periodic reading means and said clocking signal producing means for adjusting the frequency of the clocking signal based on the counted number of main memory cycles from said periodic reading means; and means coupled to said frequency adjusting means for outputting the frequency adjusted clocking signal to said processor clocking input. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method for reducing power consumption of a computer system including a processor, a producer of a clocking signal that is provided to the processor, the clocking signal having a frequency, cache memory coupled to the processor, and main memory coupled to the processor, wherein a main memory cycle is performed during write operations and cache read miss operations, the method comprising:
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counting a number of main memory cycles in the computer system; periodically determining counted number of main memory cycles; adjusting the frequency of the clocking signal from the clocking signal producer based on the counted number of main memory cycles; and outputting the frequency adjusted clocking signal to the processor. - View Dependent Claims (20, 21, 22)
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Specification