×

Graphical editor for defining memory test sequences

  • US 6,029,262 A
  • Filed: 11/25/1997
  • Issued: 02/22/2000
  • Est. Priority Date: 11/25/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. In an electronic processor, a process for defining test signals to be applied to an electronic device under test, comprising the steps of:

  • (a) accepting from a user a graphic indication of logic states for each test signal as a set of test cycles to be applied to the device under test;

    (b) accepting from a user a graphic indication that test cycles are to be repeated according to repetition parameters; and

    (c) converting the graphic indications of the logic states and repetition parameters to program code for execution on automatic test equipment, including repetition of graphically indicated test cycles.

View all claims
  • 10 Assignments
Timeline View
Assignment View
    ×
    ×