Graphical editor for defining memory test sequences

• US 6,029,262 A
• Filed: 11/25/1997
• Issued: 02/22/2000
• Est. Priority Date: 11/25/1997
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Chin, Po Wen, Medd, Jack A.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/978,083
• Time in Patent Office: 819 Days
• Field of Search: 714/724, 714/718, 714/738, 714/742, 714/744, 714/25, 702/118, 702/124, 702/125, 702/126, 345/507, 345/519, 395/701
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

Abstract

A technique for specifying test signals such as to be applied to a memory integrated circuit, by graphically displaying and editing a sequence of test cycles, together with a graphic indication of parameters that specify which of the test cycles are to be repeated. The preparation of detailed instructions for tester equipment may therefore be carried out automatically by computer software that interprets the graphic indications and generates tester microcode. As a result, knowledge of test equipment programming is not required to prepare test programs.

Claims

1. In an electronic processor, a process for defining test signals to be applied to an electronic device under test, comprising the steps of:

(a) accepting from a user a graphic indication of logic states for each test signal as a set of test cycles to be applied to the device under test;

(b) accepting from a user a graphic indication that test cycles are to be repeated according to repetition parameters; and

(c) converting the graphic indications of the logic states and repetition parameters to program code for execution on automatic test equipment, including repetition of graphically indicated test cycles.

2. A process as in claim 1 wherein step (b) additionally comprises:

accepting from the user a graphical loop indication placed adjacent a first cycle and a last cycle in a graphic depiction of a sequence of test cycles.

3. A process as in claim 2 wherein step (b) additionally comprises:

accepting from the user commands that manipulate the position and length of the loop indication, and thereby to select a first and last cycle in a repeated set of test cycles.

4. A process as in claim 1 wherein step (b) additionally comprises:

accepting from a user a specification of shading to be applied to a first cycle and a last cycle in a graphic depiction of a sequence of test cycles.

5. A process as in claim 1 wherein step (b) additionally comprises the step of:

accepting graphic indications of repetition parameters for nested repetitions of test cycles.

6. A process as in claim 1 in which step (c) converts the graphic indication of repetition parameters into program code which iterates a set of loop cycles for each of a plurality of possible storage locations in a memory device under test.

7. A process as in claim 1 wherein step (b) additionally comprises:

accepting user input specifying a number of test cycle repetitions to be executed.

8. A process as in claim 1 wherein step (b) additionally comprises:

accepting user input specifying a pattern of addresses to be applied during repetition of the test cycles.

9. A process as in claim 1 wherein the device under test is a memory component and step (b) additionally comprises:

accepting user input specifying where, in the set of test cycles, a memory row address is to change on each repetition.

10. A process as in claim 1 wherein the device under test is a memory component and step (b) additionally comprises:

accepting user input specifying where, in the set of test cycles, a memory column address is to change on each repetition.

11. A process as in claim 1 wherein the device under test is a memory component and step (c) additionally comprises the step of:

generating program code that produces test cycles which are repeated for each row of a memory device under test.

12. A process as in claim 1 wherein the graphic indication of repetition parameters additionally specifies a first sequence of test cycles, a second sequence of test cycles, and a third sequence of test cycles, the first sequence of test cycles indicating a first burst of logic signals to be applied to the device under test before the second sequence, the second sequence of cycles specifying a second burst of test cycles to be repeated, and the third sequence specifying a closing set of logic signals to be applied to the device after the repeated second bursts.

13. A process as in claim 1 additionally comprising the step of:

executing the program code on memory test equipment.

14. A process as in claim 13 in which the program code is transferred to memory test equipment located remotely from a processor which performs steps (a) through (c).

15. A process as in claim 1 wherein the test equipment comprises a plurality of parallel processors, and wherein step (c) of converting the graphic indications automatically generates program code for each of the several parallel processors.

16. A data processing system for testing an electronic device comprising:

a graphic sequence storage device, for storing a representation of visual indications of logic states for a test sequence consisting of logic states for test cycles and test cycle repetition parameters; and

a microcode generator, for parsing the representation of visual indications to determine microcode instructions which cause test equipment to generate test signals corresponding to the test cycles and looping instructions for causing the test cycles to be repeated according to the repetition parameters.

17. A system as in claim 16 additionally comprising:

test equipment for running the microcode instructions, generating the test signals in response thereto, and applying the test signals to the electronic device being tested.

18. A system as in claim 16 wherein the electronic device being tested is a memory.

19. A system as in claim 18 wherein the test cycle repetition parameters specify how a memory row address is to be changed on each repetition.

20. A system as in claim 18 wherein the test cycle repetition parameters specify how a memory column address is to be changed on each repetition.

21. A system as in claim 18 wherein the test cycle repetition parameters specify how a memory data input is to be changed on each repetition.

22. A system as in claim 18 wherein the test cycle repetition parameters specify how a memory data output is expected to change on each repetition.

23. In an electronic processor, a process for defining test signals to be applied to a synchronous dynamic random access memory (SDRAM) device under test comprising the steps of:

(a) accepting from a user a graphic indication of the logic states of test signals to be applied to the SDRAM, the test signals each comprising a set of test cycles;

the graphic indication of multiple test cycles being displayed adjacent one another;

(b) accepting from a user inputs which specify the position and length of a looping arrow located adjacent the graphic indication of multiple test signals, the looping arrow indicating a group of test cycles to be repeated according to repetition parameters;

(c) shading the group of test cycles to be repeated within the graphic indications of multiple test signals;

(d) accepting user input in a pop-up window specifying the repetition parameters;

(e) generating a microcode program for test equipment from the graphic indications of multiple test signals and the group of test cycles to be repeated; and

(f) operating the test equipment according to the microcode instructions to apply test signals to the SDRAM that repeat according to the repetition parameters.