Method for fabricating nonvolatile semiconductor memory device

• US 6,030,869 A
• Filed: 09/23/1998
• Issued: 02/29/2000
• Est. Priority Date: 09/26/1997
• Status: Expired due to Term

• Current Assignee: Pannova Semic, LLC (Vector Capital Corporation)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Tanaka, Hidenori, Kubota, Toshimoto, Maejima, Takashi, Odake, Yoshinori, Andou, Mitsuyoshi
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/158,985
• Time in Patent Office: 524 Days
• Field of Search: 438/257, 438/262, 438/263, 438/264, 438/265, 438/266, 438/301, 438/302, 438/303, 438/305, 438/306, 438/307, 438/525, 438/529, 438/595, 438/286
• US Class Current: 438/266
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a nonvolatile semiconductor memory device having a stacked gate portion, including a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode, formed over a p-type Si substrate. In the p-type Si substrate, n⁺⁺ source/drain layers and n⁺ source/drain layers, each layer containing arsenic, are formed. In the drain region, an n^- drain layer, containing phosphorus and overlapping with an entire edge of the stacked gate portion in the gate width direction, and a p layer surrounding the bottoms of the n⁺ and the n^- drain layers are provided. In such a structure, an electric field applied between the floating gate electrode and the drain is weakened and the drain-disturb characteristics are improved during writing.

Claims

1. A method for fabricating a nonvolatile semiconductor memory device, comprising the steps of:

a) forming a stacked gate portion by stacking a tunnel insulating film, a floating gate, a capacitive insulating film and a control gate in this order over a top face of a semiconductor substrate of a first conductivity type;

b) forming first and second diffusion layers each of a second conductivity type by implanting first impurity ions of the second conductivity type and second impurity ions of the second conductivity type, respectively, using the stacked gate portion as a mask in an active region of the semiconductor substrate, the first and second diffusion layers forming a portion of a drain region; and

c) forming a third diffusion layer of a first conductivity type surrounding the bottom of the portion of the drain region of the second conductivity type, which portion is formed of the first and second diffusion layers, the third diffusion layer comprising third impurity ions of the first conductivity type;

d) forming a sidewall on a side face of the stacked gate portion; and

e) forming a fourth diffusion layer of the second conductivity type to complete the drain region by implanting fourth impurity ions of the second conductivity type using the stacked gate portion and the sidewall as a mask, the drain region being formed of the first, second, and fourth diffusion layers,

wherein the first diffusion layer is formed so as to exhibit an overlap with a portion of the stacked gate portion when viewed from above, and

the fourth diffusion layer, the second diffusion layer and the first diffusion layer are formed so as to be arranged in this order along a direction from an edge of the sidewall to an edge of the gate stacked portion in a region beneath the top face of the semiconductor substrate.

2. The method of claim 1, wherein in the step b), wherein

each of the first impurity ions has a larger range than that of the second impurity ions, and

heat treatment is conducted after the first and second impurity ions are implanted, thereby to form the first and second diffusion layers.

3. The method of claim 1, further comprising a step of forming fifth and sixth diffusion layers to form a source region by implanting fifth impurity ions of the second conductivity type in the active region of the semiconductor substrate using the stacked gate portion as a mask, simultaneously with the formation of the first and second diffusion layers in the step (b).

4. The method of claim 2, wherein in the step b), a dose of the first impurity ions is set smaller than a dose of the second impurity ions.

5. The method of claim 2, wherein in the step b), at least one out of the first impurity ions and the second impurity ions are implanted immediately after the stacked gate portion has been formed.

6. The method of claim 2, wherein in the step c), the third diffusion layer of the first conductivity type is formed by implanting the third impurity ions of the first conductivity type at a tilt angle of 20 degrees or more with respect to the normal of the semiconductor substrate in accordance with large-angle-tilt ion implantation technique such that the third impurity ions are also implanted into a region under the stacked gate portion.

7. The method of claim 2, wherein the first impurity ions have a larger diffusion coefficient than that of the second impurity ions during heat treatment for activating the impurities.